NS320xx

The 320xx or NS32000 was a series of microprocessors from National Semiconductor. They were likely the first 32-bit general-purpose microprocessors on the market, but due to a number of factors never managed to become a major player. The 320xx series was also used as the basis of the Swordfish microcontroller. It was replaced by the CompactRISC architecture in mid-1990.

Architecture

NS 32000 registers
31 . . . 23 . . . 15 . . . 07 . . . 00 (bit position)
General registers
R0 Register 0
R1 Register 1
R2 Register 2
R3 Register 3
R4 Register 4
R5 Register 5
R6 Register 6
R7 Register 7
Index registers
0000 0000 SP1 Stack Pointer (user)
0000 0000 SP0 Stack Pointer (interrupt)
0000 0000 SB Static Base
0000 0000 FP Frame Pointer
0000 0000 INTBASE Interupt Base
Program counter
0000 0000 PC Program Counter
  MOD Module descriptor
Program Status Register
  15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 (bit position)
  – – – – I P S U N Z F – – L T C PSR

The processors had 8 general-purpose 32-bit registers, plus a series of special-purpose registers:

(Additional system registers not listed).

The instruction set was very much in the CISC model, with 2-operand instructions, memory-to-memory operations, flexible addressing modes, and variable-length byte-aligned instruction encoding. Addressing modes could involve up to two displacements and two memory indirections per operand as well as scaled indexing, making the longest conceivable instruction 23 bytes. The actual number of instructions was much lower than that of contemporary RISC processors.

Unlike some other processors, autoincrement of the base register was not provided; the only exception was a "top of stack" addressing mode that would pop sources and push destinations. Uniquely, the size of the displacement was encoded in its most significant bits: 0, 10 and 11 preceded 7-, 14- and 30-bit signed displacements. (Although the processors were otherwise consistently little-endian, displacements in the instruction stream were stored in big-endian order).

General-purpose operands were specified using a 5-bit field. To this could be added an index byte (specifying the index register and 5-bit base address), and up to 2 variable-length displacements per operand.

Beginnings: the 32016 and 32032

NS32008 microprocessor

The original 32016 had a 16-bit external databus, a 24-bit external address bus, and a full 32-bit instruction set. It also included a coprocessor interface, allowing coprocessors such as FPUs and MMUs to be attached as peers to the main processor. The MMU was based on demand paging Virtual Memory, which was the most unusual feature compared to the segmented memory approach used by competition, and has become the standard for how microprocessors are designed today. The architecture supported an instruction restart mechanism on a page fault, which was much cleaner than the Motorola approach to dump the internal status on a page fault, which had to be read back, before the instruction was continued. Again, the Series 32000 approach has become the standard behavior.

NS32016 microprocessor
NS32081 FPU
NS32032 microprocessor

The first chip in the series was originally called 16032, later renamed 32016 to emphasize its 32-bit internals. It became available in 1982, and may have been the first 32-bit chip to reach mass production and sale (at least according to National Semiconductor marketing). The MC68000 was released earlier with an instruction set allowing 32-bit operations, but the internal implementation was 16-bit, so 32-bit instructions would take twice the time of a 16-bit instruction. The 16032 would do 32-bit instructions as fast as 16-bit instructions. It took a long time to get the chip into production, and in 1984 the errata list still contained items specifying uncontrollable conditions that would result in the processor coming to a halt, forcing a reset. NSC changed design methodology to make it possible to get the part into production and a design system based on the language "Z" was co-developed with the University of Tel-Aviv, close to the "NSC" design centre in Herzlya, Israel. The "Z" language was similar to today's Verilog and VHDL, but had a Pascal-like syntax and was optimized for two-phase clock designs.

The instruction set resembled, but was not compatible with, that of the popular DEC VAX minicomputer.[1] It was extremely complex but mostly regular, with a large set of addressing modes. The 32016 was by some considered to be very similar to the Motorola 68000, which also used 32-bit internals with a 16-bit data bus and 24-bit address bus. This was rejected by NSC employees; one of the key marketing phrases of the time was "Elegance is Everything", comparing the highly orthogonal Series 32000 to the "kludge". One key difference was the Motorola's use of address register and data registers, with instructions only working on either address or data registers. The Series 32000 had general-purpose registers.

The original intention of National Semiconductor was to design a VAX-11 on a chip, and National took DEC to court in California (home of NSC) to ensure the legality of the design. When DEC managed to get the lawsuit moved to Massachusetts (home of DEC), the lawsuit was dropped and the Series 32000 architecture was developed.

The 32032 was introduced in 1984. It was almost completely compatible, but featured a 32-bit data bus (although keeping the 24-bit address bus) for somewhat faster performance. The 32032 was also renamed at the same time as the 16032, and the new name was 32032. There was also a 32008, a 32016 with a data bus cut down to 8-bits wide for low-cost applications. It was philosophically similar to the MC68008, and equally unpopular. Both these chips were designed to fit into the original IBM PC, but were rejected in favour of Intel's 8088.

National Semiconductor also produced related support chips like Floating Point Units (FPUs) NS32081, Memory Management Units (MMUs) NS32082, Direct Memory Access (DMA) NS32203 and Interrupt NS32202 Controllers. With the full set plus memory chips and peripherals, it was feasible to build a 32-bit computer system capable of supporting modern multi-tasking operating systems, something that had previously been possible only on expensive minicomputers and mainframes.

32332, 32532, Swordfish and others

During the 1980s, successor chips called the NS32332 and NS32532 arrived, maintaining a good degree of compatibility, with much improved reliability and performance. By then the damage to reputation had been done however, and these chips were ignored by most of the market.

In 1985, National Semi introduced the NS32332, a much improved version of the 32032. From the datasheet, the enhancements include "the addition of new dedicated addressing hardware (consisting of a high speed ALU, a barrel shifter and an address register), a very efficient increased (20 bytes) instruction prefetch queue, a new system/memory bus interface/protocol, increased efficiency slave processor protocol and finally enhancements of microcode." There was also a new NS32382 MMU, NS32381 FPU and the (very rare) NS32310 interface to a Weitek FPA. The aggregate performance boost of the NS32332 from these enhancements only made it 50 percent faster than the original NS32032, and therefore less than that of the main competitor, the MC68020.

National Semi introduced the NS32532 in early 1987. Running at 20-, 25- & 30-MHz, it was a complete redesign of the internal implementation with a five-stage pipeline, an integrated Cache/MMU and improved memory performance, making it about twice as performant as the competing MC68030 and i80386. At this stage RISC architectures were starting to make inroads, and the main competitors became the now equally dead AM29000 and MC88000, which was considered faster than the NS32532. there wasn't a new FPU; the NS32532 used the existing NS32381.(1) The NS32532 was the basis of one of the few fully realized "public domain" hardware projects (that is, resulting in an actual, useful machine running a real operating system, in this case Minix or NetBSD), the PC532.

The semi-mythical NS32732 (sometimes called NS32764), originally envisioned as the high-performance successor to the NS32532. This program never came to the market, but a derivative called Swordfish aimed at embedded systems arrived in about 1990. Swordfish had an integrated floating point unit, timers, DMA controllers and other peripherals not normally available in microprocessors. It had a 64-bit databus and was internally overclocked from 25 to 50 MHz. The chief architect of the Swordfish was Donald Alpert, who went on to manage the architectural team designing the Pentium. The Pentium internal microarchitecture is similar to the preceding Swordfish. The focus of Swordfish was high-end Postscript laserprinters, and performance was exceptional at the time. Competing solutions would produce one new page per minute, but the Swordfish demo would happily print out sixteen pages per minute supported by the laser-engine mechanics, and then on each page print out how much time it was idling, waiting for the engine to complete. The Swordfish die was huge, and it was eventually decided to drop the project altogether, and the product never went into production. The lessons from the Swordfish were used for the CompactRISC designs. In the beginning, there were both a CompactRISC-32 and a CompactRISC-16, designed using "Z". National never brought a chip to the market with the CompactRISC-32 core. National's Research department worked with the University of Michigan to develop the first synthesizable Verilog Model, and Verilog was used from the CR16C and onwards.

Versions of the older NS32000 line for low cost products such as the NS32CG16, NS32CG160, NS32FV16, NS32FX161, NS32FX164 and the NS32AM160/1/3, all based on the NS302CG16 were introduced from 1987 and onwards. These processors had some success in the laser printer and fax market, despite intense competition from AMD and Intel RISC chips. Especially the NS32CG16 should be noted. The key difference between this and the NS32C016 was the integration of the expensive TCU (Timing Control Unit) which generated the needed two-phase clock from a crystal, and the removal of the floating point coprocessor support, which freed up microcode space for the useful BitBLT instruction set, which significantly improved the performance in laser printer operations, making this 60,000 transistor chip faster than the 200,000 transistor MC68020. The NS32CG160 was the CG16 with timers and DMA peripherals, while the NS32FV/FX16x chips had extra DSP functionality on top of the CG16 BitBLT core for the Fax/Answering Machine market. They were complemented by the NS32532 based NS32GX32 later. Unlike the previous chips, there was no extra hardware. The NS32GX32 was the NS32532 without the MMU sold at an attractive price for embedded system. In the beginning, this was just a remarked chip. It is unclear if the chip was redesigned for lower-cost production.

Datasheets exist for an NS32132, apparently designed for multiprocessor systems. This was the NS32032 extended with an arbiter. The bus usage of the NS32032 was about 50 percent, owing to its very compact instruction set, or its very slow pipeline as competitors would phrase it. The NS32132 chip allowed a pair of CPUs to be connected to the same memory system, without much change of the PCB. Prototype systems were built by Diab Data AB in Sweden, but did not perform as well as the single-CPU MC68020 system designed by the same company.

Machines using the NS32000 series

M32632 FPGA implementation

In June 2015, Udo Möller released a complete Verilog implementation of an NS32000 processor on OpenCores.[2] Fully software-compatible with an NS32532 CPU with N32381 FPU, it is significantly faster when implemented on an FPGA,[3] both operating at a higher clock rate and using fewer cycles per instruction.

The clone runs the NS32k port of NetBSD.[4]

References

  1. ↑ Tilson, Michael (October 1983). "Moving Unix to New Machines". BYTE. p. 266. Retrieved 31 January 2015.
  2. ↑ M32632 32-bit Processor (OpenCores.org)
  3. ↑ M32632 Performance (cpu-ns32k.net)
  4. ↑ NetBSD (cpu-ns32k.net)

External links

Datasheets

This article is based on material taken from the Free On-line Dictionary of Computing prior to 1 November 2008 and incorporated under the "relicensing" terms of the GFDL, version 1.3 or later.

This article is issued from Wikipedia - version of the Tuesday, April 05, 2016. The text is available under the Creative Commons Attribution/Share Alike but additional terms may apply for the media files.