C-element

Delays in the naïve implementation and environment
Timing diagram of a C-element and inclusive OR gate
Majority gate realization of C-element and inclusive OR gate (a); Realizations proposed by Maevsky (b), Starodoubtsev (c) and Murphy (d)
Static implementations of two- and three input C-element [1][2][3]
Semi-static implementations of two- and multiple input C-element [3] based on the ideas from [4][5][6]
David cell (a) and its fast implementations: gate-level (b) and transistor-level (c) [7]

The Muller C-element (C-gate, Hysteresis flip-flop or sometimes, coincident flip-flop) is a small digital block widely used in design of asynchronous circuits and systems. It has been specified formally in 1955 by David E. Muller [8] and first used in ILLIAC II computer.[9] In terms of the theory of lattices, the C-element is a semimodular distributive circuit, whose operation in time is described by Hasse diagram.[10][11][12] The C-element is closely related to the Rendezvous [13] and Join [14] elements, where an input is not allowed to change twice in succession. For asynchronous circuits, where relations betweens some delays are known in advance, the requirements for C-element can be less stiff.[15] Earlier techniques for implementing the C-element [16][17] include Schmidt trigger,[18] Eccles-Jordan flip-flop and last moving point flip-flop.

Truth table and delay assumptions

For two input signals the C-element is defined by the equation y_n=x_1x_2+(x_1+x_2)y_{n-1}, which corresponds to the following truth table:

x_1 x_2 y_n
0 0 0
0 1 y_{n-1}
1 0 y_{n-1}
1 1 1

This table can be turned into a circuit using the Karnaugh map. However, the obtained implementation is naïve, since nothing is said about delay assumptions. To understand under what conditions the obtained circuit is workable, it is necessary to do additional analysis, which reveals that

Thus, the naïve implementation is correct only for slow environment.[19]

Note that the definition of C-element can be easily generalized for multiple-valued logic or even for continuous signals \text { if } x_1=x_2=...=x_m \text { then } y_n=any(x_1,x_2,...,x_m) \text { else } y_n=y_{n-1} . For example, the truth table for a balanced ternary C-element with two inputs is

x_1 x_2 y_n
-1 -1 -1
-1 0 y_{n-1}
-1 1 y_{n-1}
0 -1 y_{n-1}
0 0 0
0 1 y_{n-1}
1 -1 y_{n-1}
1 0 y_{n-1}
1 1 1

Implementations of the C-element

Depending on the requirements to the switching speed and power consumption, the C-element can be realized as a coarse- or fine-grain circuit.

Gate-level implementations

A C-element can be built using only NAND, NOR and inverter gates. Many different implementations have been proposed.[20][21][22][23][24] The so-called Maevsky's implementation [25][26][27] is a speed-independent (internally non-distributive) circuit loosely based on Varshavsky et al.,[28] which in turn, is an improved version of.[29] The 3NAND gate in this circuit can be safely replaced by two 2NAND gates. Note that sometimes it is advisable to introduce non-distributivity to increase concurrency. The C-element synthesized by Starodoubtsev et al. using Taxogram language is presented in.[30] This circuit coincides with that attributed (without reference) to Bartky in [25] and can operate without the input latch. The approach proposed in [30] is valuable by that the synthesis is done using 2NAND and 2NOR gates only. Yet another version of the C-element built on two RS latches has been synthesized by Murphy [31] using Petrify tool.

Static and semi-static implementations

In his report [8] Muller proposed to realize C-element as a majority gate with feedback. However, to alleviate hazards, which are linked with skews of internal delays, the majority gate must have as small number of transistors as possible.[32][33] Generally, C-elements with different timing assumptions [34] can be built on AND-OR-Invert (AOI) [35][36] or its dual, OR-AND-Invert (OAI) gate [37][38] and inverter.

Note that connecting an additional majority gate to the inverted output of C-element, we obtain inclusive OR (EDLINCOR) function:[39][40] z_n=x_1x_2+(x_1+x_2)\overline{y_n}. Note also that some simple asynchronous circuits like pulse distributors [41] can be built solely on majority gates.

Since the majority gate is a particular case of threshold gate, any of known realizations of threshold gate [42] can in principle be used for building a C-element. In the multiple-valued case however, connecting the output of majority gate to one or several inputs may have no desirable effect. For example, using the ternary majority function defined as:[43]

y=\left\{\begin{matrix} +1 \text { if } x_1+x_2+x_3\geqslant +1;\\ 0 \text { if } x_1+x_2+x_3=0;\\ -1 \text { if } x_1+x_2+x_3\leqslant -1; \end{matrix}\right.

does not lead to the ternary C-element specified by the truth table, if the sum x_1+x_2+x_3 is not split into pairs. However, even without such a splitting two ternary majority functions are suitable for building a ternary inclusive OR gate.

Semi-static C-element stores its previous state using two cross-coupled inverters, similar to an SRAM cell. One of the inverters is weaker than the rest of the circuit, so it can be overpowered by the pull-up and pull-down networks. If both inputs are 0, then the pull-up network changes the latch's state, and the C-element outputs a 0. If both inputs are 1, then the pull-down network changes the latch's state, making the C-element output a 1. Otherwise, the input of the latch is not connected to either V_{dd} or ground, and so the weak inverter dominates and the latch outputs its previous state.

Note that both the Maevsky and Starodoubtsev circuits are based actually on so-called David cell.[44] Its fast transistor-level implementation is used in the semi-static C-element proposed in.[45] Yet another semi-static circuit using pass transistors has been proposed in.[46]

There are also versions of semi-static C-element built on devices with negative differential resistance (NDR).[47][48] It should be noted however, that NDR is usually defined for small signal. So, it is difficult to expect that such a C-element will operate in full range of voltages or currents.

Other modern technologies suitable for realizing asynchronous primitives including C-element, are carbon nanotubes,[49] single electron tunneling devices,[50] quantum dots [51] and molecular nanotechnology.[52]

Advanced topics

Some speed-independent approaches [53][54] assume that zero-delay input inverters are available on all gates, which is a violation of true speed-independence but is fairly safe in practice. Other examples of using this assumption can be found.[55][56][57]

References

  1. ↑ I. E. Sutherland, "Micropipelines," Communications of the ACM, vol. 32, no. 6, pp. 720-738, 1989.
  2. ↑ C. H. van Berkel, "Beware the isochronic fork," Report UR 003/91, Philips Research Laboratories, 1991.
  3. 1 2 V. B. Marakhovsky, Logic design of asynchronous circuits. Slides on the course. CS&SE Department, SPbPU.
  4. ↑ V. I. Varshavsky, "β-driven threshold elements," IEEE Great Lakes Symposium on VLSI 1998, pp. 52-58.
  5. ↑ V. I. Varshavsky, N. M. Kravchenko, V. B. Marakhovsky, B. S. Tsirlin, "H flip-flop," USSR author's certificate SU1562964, Jul. 5, 1990.
  6. ↑ K. J. Schultz, R. J. Francis, K. C. Smith, "Ganged CMOS: trading standby power for speed," IEEE Journal of Solid-State Circuits, vol. 25, no. 3, pp. 870-873, 1990.
  7. ↑ A. Bystrov, A. Yakovlev, Asynchronous circuit synthesis by direct mapping: Interfacing to environment. Technical Report, CS Department, University of Newcastle upon Tyne, October 2001.
  8. 1 2 D. E. Muller, Theory of asynchronous circuits. Report no. 66, Digital Computer Laboratory, University of Illinois at Urbana-Champaign, 1955.
  9. ↑ H. C. Breadley, "ILLIAC II — A short description and annotated bibliography," IEEE Transactions on Electronic Computers, vol. EC-14, no. 3, pp. 399-403, 1965.
  10. ↑ D. E. Muller and W. S. Bartky, "A theory of asynchronous circuits," Int. Symposium on the Switching Theory in Harvard University, pp. 204-243, 1959.
  11. ↑ W. J. Poppelbaum, Introduction to the Theory of Digital Machines. Math., E.E. 294 Lecture Notes, University of Illinois at Urbana-Champaign.
  12. ↑ J. Gunawardena, "A generalized event structure for the Muller unfolding of a safe net," Int. Conference on Concurrency Theory (CONCUR) 1993, pp. 278-292.
  13. ↑ M. J. Stucki, S. M. Ornstein, W. A. Clark, "Logical design of macromodules," in Proceedings of AFIPS 1967, pp. 357-364.
  14. ↑ J. C. Ebergen, J. Segers, I. Benko, "Parallel Program and Asynchronous Circuit Design," Workshops in Computing, pp. 50-103, 1995.
  15. ↑ H. Park, A. He, M. Roncken and X. Song, "Semi-modular delay model revisited in context of relative timing," IET Electronics Letters, vol. 51, no. 4, pp. 332-334, 2015.
  16. ↑ Technical Progress Report, Jan. 1959, University of Illinois at Urbana-Champaign.
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  21. ↑ B. S. Tsirlin, "Multiple input H flip-flop," USSR author's certificate SU1162019, Jun. 15, 1985
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  24. ↑ G. S. Brailovsky, L. Ya. Rozenblyum, B. S. Tsirlin, "H flip-flop," USSR author's certificate SU1432733, Oct, 23, 1988
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  27. ↑ S. Golubcovs, A. Alekseyev, A. Mokhov, A. Yakovlev, "Asynchronous circuit development with Workcraft," Technical Report NCL-EECE-MSD-TR-2011-174, University of Newcastle upon Tyne, 2011
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  30. 1 2 N. A. Starodoubtsev, S. A. Bystrov, "Monotonic behavior refinement for synthesis of two-input-gate asynchronous circuits," IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS) 2004, vol. I, pp. I-521-524.
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