CompactPCI PlusIO

Introduction

CompactPCI PlusIO is an extension to the PICMG 2.0 CompactPCI industrial standard for modular computer systems.[1] CompactPCI PlusIO was officially adopted by the PCI Industrial Computer Manufacturers Group PICMG as PICMG 2.30 CompactPCI PlusIO in November 2009. Being 100% compatible with CompactPCI, PICMG 2.30 defines a migration path to the future CompactPCI Serial standard. It defines a fixed rear I/O pin assignment that focuses on modern, fast serial point-to-point connections. The new technology succeeding parallel CompactPCI comprises both CompactPCI Serial and CompactPCI PlusIO.

History

The CompactPCI standard uses one main bus connector, J1, and defines user I/O pins and a 64-bit extension for the legacy PCI bus on connector J2. J1 and J2 are the only connectors on 3U single Eurocards. The CompactPCI definition for 6U double Eurocards includes additional connectors (J3, J4, J5) for rear I/O. A true rear I/O standard, however, exists only for J3 – through the PICMG 2.16 CompactPCI Packet Switching Backplane specification[2] that defines Ethernet interfaces at the backplane of 6U cards. Fast serial point-to-point connections have become the state-of-the-art technology and are gradually replacing the classic bus architecture in computers.[3] Also, 3U-based systems are very popular because of their small footprint. This is especially true for modular embedded applications, for example in the field of communications. As a result, several manufacturers tried to implement their own rear I/O concepts using the J2 connector, but had no standard to make their J2 pin assignments compatible with other cards. Another approach to realize serial high-speed interfaces were so-called switched fabrics, which used additional switches and bridges to connect to each other. This involved higher costs and still provided solutions that were too specialized to be compatible with each other. The CompactPCI standard as it is does not offer a standardized solution for the kind of modular connectivity requested for the future. The additional PICMG 2.30 CompactPCI PlusIO specification provides this connectivity on the well-known platform of CompactPCI. It stays compatible with but extends the existing standard by a new definition of the rear J2 connector, adding a number of serial interfaces to provide fast and standardized rear I/O also on 3U format. Through these serial point-to-point connections, CompactPCI PlusIO also bridges the gap between parallel CompactPCI and the serial CompactPCI Serial standard.

Interfaces

PICMG 2.30 CompactPCI PlusIO standardizes the following interfaces at the rear J2 connector:

Backplane Connectors

The PICMG 2.30 extension introduces a new J2 connector type on the plug-in board, an Ultra Hard Metric (UHM) connector with virtual coaxial box shielding technology, which reduces crosstalk at high speeds. This connector supports high frequencies of 5 Gbit/s, even when mated with the CompactPCI-standard unshielded 2-mm hard-metric headers. The matching P2 backplane connector remains the same as for CompactPCI, as do the J1/P1 connectors.

Compatibility with Legacy CompactPCI and CompactPCI Serial

PICMG 2.30 gives the J2 pins a fixed interface functionality. This makes 64-bit bus communication impossible. The new J2 connector type itself is 100% compatible with the legacy one. The J1 bus connector conforms with the CompactPCI definition. In all, CompactPCI PlusIO is 100% compatible with legacy 32-bit CompactPCI in 3U and 6U format (single and double Eurocards). At the same time, its serial rear I/O connectivity and higher-speed connector form a bridge towards future CompactPCI Serial system architecture. Hybrid backplanes support several cards of the three different standards PICMG 2.0, 2.30, and CPCI-S.0.[4][5]

See also

References

  1. ↑ PICMG 2.0
  2. ↑ PICMG 2.16
  3. ↑ "Teaching old dogs new serial I/O tricks on CompactPCI". Embedded.com. 2011-04-19. Retrieved 2015-09-25.
  4. ↑ "Teaching old dogs new serial I/O tricks on CompactPCI". Embedded.com. 2011-04-19. Retrieved 2015-09-25.
  5. ↑ "Mixed Doubles: CompactPCI Serial and CompactPCI 2.0". Intel. 2011-06-27. Retrieved 2015-09-25.

External links

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