Cycles per instruction

In computer architecture, cycles per instruction (aka clock cycles per instruction, clocks per instruction, or CPI) is one aspect of a processor's performance: the average number of clock cycles per instruction for a program or program fragment.^[1] It is the multiplicative inverse of instructions per cycle.

Definition

Cycles Per Instruction is defined by the following:

$CPI = \frac{\Sigma (IIC)(CCI) }{IC}$

Where IIC is the number of instructions for a given instruction type, CCI is the clock-cycles for a given instruction type, IC is the total instruction count. The summation sums over all instruction types for a given benchmarking process.

Explanation

Let us assume a classic RISC pipeline, with the following 5 stages:

1. Instruction fetch cycle (IF).
2. Instruction decode/Register fetch cycle (ID).
3. Execution/Effective address cycle (EX).
4. Memory access (MEM).
5. Write-back cycle (WB).

Each stage requires one clock cycle and an instruction passes through the stages sequentially. Without pipelining, a new instruction is fetched in stage 1 only after the previous instruction finishes at stage 5, therefore the number of clock cycles it takes to execute an instruction is 5 (CPI = 5 > 1). In this case, the processor is said to be subscalar. With pipelining, a new instruction is fetched every clock cycle by exploiting instruction-level parallelism, therefore, since one could theoretically have 5 instructions in the 5 pipeline stages at once (one instruction per stage), a different instruction would complete stage 5 in every clock cycle and on average the number of clock cycles it takes to execute an instruction is 1 (CPI = 1). In this case, the processor is said to be scalar.

With a single-execution-unit processor, the best CPI attainable is 1. However with a multiple-execution-unit processor, one may achieve even better CPI values (CPI < 1). In this case, the processor is said to be superscalar. To get better CPI values without pipelining, the number of execution units must be greater than the number of stages. For example, with 6 executions units, 6 new instructions are fetched in stage 1 only after the 6 previous instructions finish at stage 5, therefore on average the number of clock cycles it takes to execute an instruction is 5/6 (CPI = 5/6 < 1). To get better CPI values with pipelining, there must be at least 2 execution units. For example, with 2 executions units, 2 new instructions are fetched every clock cycle by exploiting instruction-level parallelism, therefore 2 different instructions would complete stage 5 in every clock cycle and on average the number of clock cycles it takes to execute an instruction is 1/2 (CPI = 1/2 < 1).

Examples

Example 1

For the multi-cycle MIPS, there are 5 types of instructions:

• Load (5 cycles)
• Store (4 cycles)
• R-type (4 cycles)
• Branch (3 cycles)
• Jump (3 cycles)

If a program has:

• 50% load instructions
• 15% R-type instructions
• 25% store instructions
• 8% branch instructions
• 2% jump instructions

then, the CPI is:

$\text{CPI} = \frac{5 \times 50 + 4 \times 15 + 4 \times 25 + 3 \times 8 + 3 \times 2}{100} = 4.4$

Example 2

^[2] A 400-MHz processor was used to execute a benchmark program with the following instruction mix and clock cycle count:

Instruction type	Instruction count	Clock cycle count
Integer arithmetic	45000	1
Data transfer	32000	2
Floating point	15000	2
Control transfer	8000	2

Determine the effective CPI, MIPS rate, and execution time for this program.

Total instruction count = 100000

$\text{CPI} = \frac{45000 \times 1 + 32000 \times 2 + 15000 \times 2 + 8000 \times 2}{100000} = \frac{155000}{100000} = 1.55$

$\text{Effective processor performance} = \text{MIPS} = \frac{\text{clock frequency}}{\text{CPI} \times 1000000} = \frac{400 \times 1000000}{1.55 \times 1000000} = 258 \, \text{MIPS}$

Therefore:

$\text{Execution time}(T) = \text{CPI} \times \text{Instruction count} \times \text{clock time} = \frac{\text{CPI} \times \text{Instruction Count}}{\text{frequency}} = \frac{1.55 \times 1000000}{400 \times 1000000} = \frac{1.55}{400} = 3.875 \, \text{ms}$

See also

• MIPS
• Instructions per cycle (IPC)
• Instructions per second (IPS)
• Cycle per second (Hz)
• Megahertz myth
• The benchmark article provides a useful introduction to computer performance measurement for those readers interested in the topic.

References

1. Patterson, David A.; Hennessy, John L. Computer Organization and Design: The Hardware/Software Interface.
2. Advanced Computer Architecture by Kai Hwang, Chapter 1, Exercise Problem 1.1