Dennard scaling

Dennard scaling, also known as MOSFET scaling, is a scaling law based on a 1974 paper co-authored by Robert H. Dennard, after whom it is named.[1] Originally formulated for MOSFETs, it states, roughly, that as transistors get smaller their power density stays constant, so that the power use stays in proportion with area: both voltage and current scale (downward) with length.[2]

Relation with Moore's law and computing performance

Dennard scaling relates to Moore's law (which postulates a reduction in the size of transistors leading to more and more transistors per chip at the cost-effective optimum) and the claims that the performance per watt of computing is growing exponentially at roughly the same rate. This is closely related to Koomey's law, which says that performance per watt in computing has been doubling every 1.57 years (somewhat faster than the doubling period of Moore's law, which is about 1.8 years).[3]

Breakdown of Dennard scaling around 2006

The dynamic (switching) power consumption of CMOS circuits is proportional to frequency.[4] Historically, the transistor power reduction afforded by Dennard scaling allowed manufacturers to drastically raise clock frequencies from one generation to the next without significantly increasing overall circuit power consumption.

Since around 2005–2007 Dennard scaling appears to have broken down. As of 2016, transistor counts in integrated circuits are still growing, but the resulting improvements in performance are more gradual than the speed-ups resulting from significant frequency increases.[2][5] The primary reason cited for the breakdown is that at small sizes, current leakage poses greater challenges, and also causes the chip to heat up, which creates a threat of thermal runaway and therefore further increases energy costs.[2][5]

The breakdown of Dennard scaling and resulting inability to increase clock frequencies significantly has caused most CPU manufacturers to focus on multicore processors as an alternative way to improve performance. An increased core count benefits many (though by no means all) workloads, but the increase in active switching elements from having multiple cores still results in increased overall power consumption and thus worsens CPU power dissipation issues.[6][7] The end result is that only some fraction of an integrated circuit can actually be active at any given point in time without violating power constraints. The remaining (inactive) area is referred to as dark silicon.

See also

References

  1. ↑ Dennard, Robert H.; Gaensslen, Fritz; Yu, Hwa-Nien; Rideout, Leo; Bassous, Ernest; LeBlanc, Andre (October 1974). "Design of ion-implanted MOSFET's with very small physical dimensions" (PDF). IEEE Journal of Solid State Circuits SC–9 (5).
  2. 1 2 3 McMenamin, Adrian (April 15, 2013). "The end of Dennard scaling". Retrieved January 23, 2014.
  3. ↑ Greene, Katie (September 12, 2011). "A New and Improved Moore's Law: Under “Koomey’s law,” it’s efficiency, not power, that doubles every year and a half.". Technology Review. Retrieved January 23, 2014.
  4. ↑ "CMOS Power Consumption and CPD Calculation" (PDF). Texas Instruments. June 1997. Retrieved March 9, 2016.
  5. 1 2 Bohr, Mark (January 2007). "A 30 Year Retrospective on Dennard's MOSFET Scaling Paper" (PDF). Solid-State Circuits Society. Retrieved January 23, 2014.
  6. ↑ Esmaeilzedah, Hadi; Blem, Emily; St. Amant, Renee; Sankaralingam, Kartikeyan; Burger, Doug. "Dark Silicon and the end of multicore scaling" (PDF).
  7. ↑ Hruska, Joel (February 1, 2012). "The death of CPU scaling: From one core to many — and why we’re still stuck". ExtremeTech. Retrieved January 23, 2014.
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