Josh Fisher

Josh Fisher
Josh Fisher in 2014
Born	July 22, 1946 [1] Bronx, NY, USA [1]
Fields	Computer Architecture, Compiling, Embedded Systems
Institutions	Yale University, Multiflow Computer, Hewlett-Packard Laboratories (retired)
Alma mater	Courant Institute of Mathematical Sciences (New York University)
Known for	The Invention of VLIW Architectures, Instruction-level Parallelism, Trace Scheduling, Co-Founder of Multiflow Computer
Notable awards	Eckert-Mauchly Award, (IEEE/ACM 2003) B. Ramakrishna Rau Award (IEEE-CS 2012) Connecticut Entrepreneur of the Year (1987) Presidential Young Investigator's Award (NSF 1984)

Joseph A "Josh" Fisher is an American computer scientist noted for his work on VLIW architectures, compiling, and instruction-level parallelism, and for the founding of Multiflow Computer. He is a Hewlett-Packard Senior Fellow (Emeritus).^[2]

Biography

Fisher holds a BA (1964) in mathematics (with honors) from New York University and obtained a Master's and PhD degree (1979) in Computer Science from The Courant Institute of Mathematics of New York University.^[1]

Fisher joined the Yale University Department of Computer Science in 1979 as an assistant professor, and was promoted to associate professor in 1983. In 1984 Fisher left Yale to found Multiflow Computer with Yale colleagues John O'Donnell and John Ruttenberg. Fisher joined HP Labs upon the closing of Multiflow in 1990. He directed HP Labs in Cambridge, MA USA from its founding in 1994, and became an HP Fellow (2000) and then Senior Fellow (2002) upon the inception of those titles at Hewlett-Packard. Fisher retired from HP Labs in 2006.

Fisher is married (1967) to Elizabeth Fisher; they have a son, David Fisher, and a daughter, Dora Fisher.^[3]

Work

Trace Scheduling

In his Ph.D. dissertation, Fisher created the Trace Scheduling compiler algorithm and coined the term Instruction-level parallelism to characterize VLIW, superscalar, dataflow and other architecture styles that involve fine-grained parallelism among simple machine-level instructions. Trace scheduling was the first practical algorithm to find large amounts of parallelism between instructions that occupied different basic blocks. This greatly increased the potential speed-up for instruction-level parallel architectures.

The VLIW architecture style

Because of the difficulty of applying trace scheduling to idiosyncratic systems (such as 1970s-era DSPs) that in theory should have been suitable targets for a trace scheduling compiler, Fisher put forward the VLIW architectural style. VLIWs are normal computers, designed to run compiled code and used like ordinary computers, but offering large amounts of instruction-level parallelism scheduled by a trace scheduling or similar compiler. VLIWs are now used extensively, especially in embedded systems. The most popular VLIW cores have sold in quantities of several billion processors. ^{[4] [5] [6] [7]}

Multiflow Computer

Multiflow was founded to commercialize trace scheduling and VLIW architectures, then widely thought to be impractical. Multiflow's technical success and the dissemination of its technology and people had a great effect on the future of computer science and the computer industry.^[3]

Awards and honors

• 1984 NSF Presidential Young Investigator's Award. (This award was meant to persuade promising faculty to stay at universities; financial grant to Yale University declined due to Fisher's leaving to start Multiflow.)
• 1987 Eli Whitney Connecticut Entrepreneur of the Year.
• 2003 Eckert-Mauchly Award given by The IEEE Computer Society and The Association for Computing Machinery, in recognition of 25 years of seminal contributions to instruction-level parallelism, pioneering work on VLIW architectures, and the formulation of the Trace Scheduling compilation technique. The Eckert-Mauchly is known as the computer architecture community’s highest award.
• 2012 B. Ramakrishna Rau Award given by The IEEE Computer Society for the development of trace scheduling compilation and pioneering work in VLIW (Very Long Instruction Word) architectures.

Writings

• Joseph A Fisher, Paolo Farabochi and Cliff Young: Embedded Computing: A VLIW Approach to Architecture, Compilers and Tools. Elsevier/Morgan Kaufmann, 2004.
• Joseph A Fisher: Trace Scheduling: A Technique for Global Microcode Compaction IEEE Trans. Computers, 30(7):478-490, 1981.
• Joseph A. Fisher: Very Long Instruction Word architectures and the ELI-512 ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture, Pages 140-150, ACM, New York, NY, USA. Retrospective, 25 Years of ISCA, ACM, 1998.
• Joseph A. Fisher, John R. Ellis, John C. Ruttenberg, Alexandru Nicolau: Parallel Processing: A Smart Compiler and a Dumb Machine Symp. Compiler Construction, 1984: 37-47. Retrospective, Best of PLDI, ACM SIGPLAN Notices, 39(4):112, 2003.
• B. Ramakrishna Rau, Joseph A. Fisher: Instruction-level parallel processing: history, overview, and perspective The Journal of Supercomputing - Special issue on instruction-level parallelism, Volume 7 Issue 1-2, May 1993. Also published by Kluwer Academic Publishers Hingham, MA, USA.

References

1. Joseph A Fisher vita
2. Hewlett-Packard Senior Fellow Biography.
3. http://www.MultiflowTheBook.com Multiflow Computer: A Startup Odyssey.
4. The Hexagon VLIW The Hexagon is a 4-issue VLIW.
5. Qualcomm Announces Its 2012 Superchip: 28nm Snapdragon S4, 10/12/2011 by John Oram. The article states that Hexagons have been in Snapdragon chips since 2006.
6. Estimate of Snapdragon volumes.
7. The ST231. The ST231 is rumored to have been sold in quantities upwards of 1 billion cores, used mostly in digital video.

External links

• Elizabeth Fisher: Multiflow Computer: A Startup Odyssey. CreateSpace, 2013.
• IEEE: The VLIW Architecture of Joseph A. Fisher, Part 1 Solid-State Circuits Magazine, IEEE, 2009, Volume: 1 , Issue: 2. Also Part 2