List of Intel CPU microarchitectures

The following is a partial list of Intel CPU microarchitectures. The list is incomplete.

x86 microarchitectures

Year	Microarchitecture	Pipeline stages	max. Clock
1989	486 (80486)	3	100 MHz	30 ns
1993	P5 (Pentium)	5	300 MHz	16.7 ns
1995	P6 (Pentium II)	14 (17 with load & store/retire)	450 MHz	31 ns
1999	P6 (Pentium III)	12 (15 with load & store/retire)	450~1400 MHz
2000	NetBurst (Pentium 4)	20	800~3000 MHz
2003	Pentium M	10 (12 with fetch/retire)	400~1000 MHz
2004	Prescott	31	3800 MHz
2006	Intel Core	12 (14 with fetch/retire)	3000 MHz	4 ns
2008	Nehalem	20	3000 MHz
2008	Bonnell	16 (20 with prediction miss)	2100 MHz
2011	Sandy Bridge	14 (16 with fetch/retire)	3600 MHz
2013	Haswell	14 (16 with fetch/retire)	≈4000 MHz	3.5 ns
2015	Skylake	14 (16 with fetch/retire)	≈4000 MHz

• 8086: first x86 processor; initially a temporary substitute for the iAPX 432 to compete with Motorola, Zilog, and National Semiconductor and to top the successful Z80.
• 186: included a DMA controller, interrupt controller, timers, and chip select logic.
• 286: first x86 processor with protected mode including segmentation based virtual memory management. Performance improved by a factor of 3...4 over 8086.
• i386: first 32-bit x86 processor. Introduced paging on top of segmentation which is the most commonly used memory protection technology in modern operating systems ever since.
• i486: Intel's second generation of 32-bit x86 processors, introduced built-in floating point unit (FPU), 8 KB on-chip L1 cache, and pipelining.
• P5: original Pentium microprocessors, first x86 processor with super scaling feature, branch prediction and RISC micro-uop decode scheme.
• P6: used in Pentium Pro, Pentium II, Pentium II Xeon, Pentium III, and Pentium III Xeon microprocessors. First x86 processor to support SIMD instruction with XMM register implemented, integrated register renaming and Out of Order execution.
  • Pentium M: updated version of Pentium III's P6 microarchitecture designed from the ground up for mobile computing and first x86 to support micro-op fusion and smart cache.
  • Enhanced Pentium M: updated, dual core version of the Pentium M microarchitecture used in Core microprocessors, first x86 to have shadow register architecture and speed step technology.
• NetBurst: used in Pentium 4, Pentium D, and some Xeon microprocessors. Commonly referred to as P7 although its internal name was P68 (P7 was used for Itanium). Later revisions were the first to feature Intel's x86-64 architecture, enhanced branch prediction and trace cache.
• Core: reengineered P6-based microarchitecture used in Core 2 and Xeon microprocessors, built on a 65 nm process, supporting x86-64 level SSE instruction and macro-op fusion&enhanced micro-op fusion with wider front end and decoder, larger Out of Order core and renamed register, support loop stream detector and large shadow register file.
  • Penryn: 45 nm shrink of the Core microarchitecture with larger cache, higher FSB and clock speeds, and SSE4.1 instructions, support xop and F/SAVE&F/STORE instruction and enhance register alias table and larger integer register file.
• Nehalem: released November 17, 2008, built on a 45 nm process and used in the Core i7, Core i5, Core i3 microprocessors. Incorporates the memory controller into the CPU die.
  • Westmere: 32 nm shrink of the Nehalem microarchitecture with several new features.
• Sandy Bridge: released January 9, 2011, built on a 32 nm process and used in the Core i7, Core i5, Core i3 second generation microprocessors, and in Pentium B9XX and Celeron B8XX series. Formerly called Gesher but renamed in 2007.^[1] First x86 to introduce 256 bit AVX instruction set and implementation of YMM register.
  • Ivy Bridge: 22 nm shrink of the Sandy Bridge microarchitecture released April 28, 2012.
• Haswell: 22 nm microarchitecture, released June 3, 2013.
  • Broadwell: 14 nm shrink of the Haswell microarchitecture, released in September 2014. Formerly called Rockwell.
• Skylake: new 14 nm microarchitecture, released August 5, 2015.
  • Kaby Lake: expected in 2016, breaking Intel's Tick-Tock schedule due to delays with the 10 nm process.
  • Cannonlake: 10 nm shrink of Kaby Lake. Formerly called Skymont.
• Ice Lake: new 10 nm microarchitecture, expected in 2018.
  • Tiger Lake: an update of Ice Lake, serving as "semi-Tock" of the Intel's Tick-Tock strategy, expected in 2019.
• Larrabee: multi-core in-order x86-64 updated version of P5 microarchitecture, with wide SIMD vector units and texture sampling hardware for use in graphics. Cores derived from this microarchitecture are called MIC (Many Integrated Core).
• Bonnell: 45 nm, low-power, in-order microarchitecture for use in Atom processors.
  • Saltwell: 32 nm shrink of the Bonnell microarchitecture.
• Silvermont: 22 nm, out-of-order microarchitecture for use in Atom processors, released May 6, 2013.
  • Airmont: 14 nm shrink of the Silvermont microarchitecture.
• Goldmont: 14 nm Atom microarchitecture.^[2][3]

Itanium microarchitectures

• Merced microarchitecture: original Itanium microarchitecture. Used only in the first Itanium microprocessors.
• McKinley microarchitecture: enhanced microarchitecture used in the first two generations of the Itanium 2 microprocessor.
• Montecito microarchitecture: enhanced McKinley microarchitecture used in the Itanium 2 9000- and 9100-series of processors. Added dual core, coarse multithreading, and other improvements.
• Tukwila microarchitecture: enhanced microarchitecture used in the Itanium 9300 series of processors. Added quad core, SMT, an integrated memory controller, QuickPath Interconnect, and other improvements.
• Poulson microarchitecture: Itanium processor featuring a new microarchitecture.^[4]
• Kittson microarchitecture: future Itanium processors

Roadmap

Architectural change	Fabrication process	Micro​architecture	Codenames	Release date	Processors
					8P/4P Server/WS	4P/2P Server/WS	Enthusiast/​WS	Desktop	Mobile	Marketing names
Tick Manufacturing Technology	65 nm	P6, NetBurst	Presler, Cedar Mill, Yonah	2006-01-05			Presler	Cedar Mill	Yonah	Core Pentium 4 Pentium D Pentium M Pentium Dual-Core Celeron Xeon
Tock New Microarchitecture		Core	Merom[5]	2006-07-27[6]	Tigerton	Woodcrest Clovertown	Kentsfield	Conroe	Merom	Core 2 Pentium Dual-Core Pentium Celeron Dual-Core Celeron Celeron M Xeon
Tick Manufacturing Technology	45 nm		Penryn	2007-11-11[7]	Dunnington	Harpertown	Yorkfield	Wolfdale	Penryn
Tock New Microarchitecture		Nehalem	Nehalem	2008-11-17[8]	Beckton	Gainestown	Bloomfield	Lynnfield	Clarksfield	Core i3 Core i5 Core i7 Pentium Celeron Xeon
Tick Manufacturing Technology	32 nm		Westmere	2010-01-04[9][10]	Westmere-EX	Westmere-EP	Gulftown	Clarkdale	Arrandale
Tock New Microarchitecture		Sandy Bridge	Sandy Bridge	2011-01-09[11]	(Skipped)[12]	Sandy Bridge-EP	Sandy Bridge-E	Sandy Bridge	Sandy Bridge-M	Core i3 Core i5 Core i7	2nd Generation Intel Core
										Pentium Celeron Xeon
Tick Manufacturing Technology	22 nm[13]		Ivy Bridge	2012-04-29	Ivy Bridge-EX[14]	Ivy Bridge-EP[14]	Ivy Bridge-E[15]	Ivy Bridge	Ivy Bridge-M	Core i3 Core i5 Core i7	3rd Generation Intel Core
										Pentium Celeron Xeon
Tock New Microarchitecture		Haswell	Haswell	2013-06-02	Haswell-EX	Haswell-EP	Haswell-E	Haswell-DT[16]	Haswell-MB (notebooks) Haswell-LP (ultrabooks)[16]	Core i3 Core i5 Core i7	4th Generation Intel Core
										Pentium Celeron Xeon
Refresh			Haswell Refresh, Devil's Canyon[17]	2014-06						i5-4690K i7-4790K
Tick Manufacturing Technology	14 nm[13]		Broadwell[18]	2014-09-05	Broadwell-EX [19]	Broadwell-EP [19]				Core i3 Core i5 Core i7	5th Generation Intel Core
										Core M Pentium Celeron Xeon
Tock New Microarchitecture		Skylake[18]	Skylake[18]	2015-08-05[20]	Skylake-EX	Skylake-EP				Core i3 Core i5 Core i7	6th Generation Intel Core
										Core M Pentium Celeron Xeon
Refresh[21][22] (semi-Tock)[23]			Kaby Lake[24]	2016
Tick	10 nm[25]		Cannonlake	2017
Tock		Ice Lake[23]	Ice Lake	2018
semi-Tock[23]			Tiger Lake[23]	2019
Tick	7 nm[25]			?
Tock				?
Tick	5 nm[25]			?
Tock				?

Atom Roadmap[26]
	Fabrication process	Microarchitecture	Release date	Processors/SoCs
				MID, Smartphone	Tablet	Netbook	Nettop	Embedded	Server	Communication	CE
Tick	45 nm	Bonnell	2008	Silverthorne	N/A	Diamondville		Tunnel Creek & Stellarton	N/A		Sodaville
Tock			2010	Lincroft		Pineview					Groveland
Tick	32 nm	Saltwell	2011	Medfield (Penwell & Lexington) & Clover Trail+ (Cloverview)	Clover Trail (Cloverview)	Cedar Trail (Cedarview)		Unknown	Centerton & Briarwood	Unknown	Berryville
Tick	22 nm	Silvermont	2013	Merrifield (Tangier) [27] & Moorefield (Anniedale)[28] & Slayton	Bay Trail-T (Valleyview)	Bay Trail-M (Valleyview)	Bay Trail-D (Valleyview)	Bay Trail-I (Valleyview)	Avoton	Rangeley	Unknown
Tick	14 nm[26]	Airmont	2014	Binghamton & Riverton	Cherry Trail-T (Cherryview) [29]	Braswell [30]			Denverton	Unknown	Unknown
Tock		Goldmont[2][3]	2016	Morganfield (Broxton)[31]	Willow Trail (Willowview)	Apollo Lake	Unknown	Unknown	Unknown	Unknown	Unknown

See also

• List of AMD CPU microarchitectures
• Marvell Technology Group XScale microarchitecture

References

1. "An Update On Our Graphics-related Programs". May 25, 2010.
2. "Intel Software Development Emulator".
3. ""Goldmont"- the sequel to Silvermont Atom?".
4. Anton Shilov (June 19, 2007). "Intel Plans to change Itanium Micro-Architecture". X-bit Labs. Retrieved 2007-10-05.
5. Crothers, Brooke (2009-02-10). "Intel moves up rollout of new chips | Nanotech - The Circuits Blog - CNET News". News.cnet.com. Retrieved 2014-02-25.
6. Intel CEO: Latest Platforms, Processors Form New Foundations For Digital Entertainment And Wireless Computing, Intel Unveils World's Best Processor
7. Intel Unveils 16 Next-Generation Processors, Including First Notebook Chips Built on 45nm Technology
8. Intel Launches Fastest Processor on the Planet
9. http://download.intel.com/pressroom/kits/32nm/westmere/Mark_Bohr_32nm.pdf
10. Revolutionizing How We Use Technology—Today and Beyond
11. Intel Sandy Bridge chip coming January 5
12. Intel Ivy Bridge CPU Range Complete by Next Year
13. 22nm technology. May 2011
14. http://vr-zone.com/articles/ivy-bridge-ep-and-ex-coming-up-in-a-year-s-time--the-multi-socket-platform-heaven/15488.html
15. Ivy Bridge-E Delayed Until Second Half of 2013
16. "Leaked specifications of Haswell GT1/GT2/GT3 IGP". Tech News Pedia. 2012-05-20. Retrieved 2014-02-25.
17. "Devils Canyon mit bis zu 4,4 GHz, ohne verlöteten Deckel". golem.de. Jun 3, 2014.
18. After Intel's Haswell comes Broadwell - SemiAccurate
19. Intel to release 22-core Xeon E5 v4 “Broadwell-EP” late in 2015
20. The wait for Skylake is almost over, first desktop chips likely to hit August 5
21. "Intel 14nm Kaby Lake “Skylake Refresh” Platform Detailed – Launching in 2H 2016, 256 MB eDRAM H-Series and 91W K-Series Unveiled". wccftech.com. July 2015. The Kaby Lake platform will be similar to Skylake platform that launches this year and will act as a platform refresher
22. "Intel Releasing 14nm Kaby Lake Processor in 2016 Ahead of 10nm Cannonlake". legitreviews.com. 2015-07-08. We have long known that Intel was planning a ‘Skylake Refresh’ that has always been on the roadmap between Skylake and Cannonlake, but it appears that refresh might be going by the code name Kaby lake now.
23. "Intel’s Cannonlake CPUs To Be Succeeded By 10nm Ice Lake Family in 2018 and 10nm Tiger Lake Family in 2019". WCCFTech. 2016-01-20.
24. "Intel confirms tick-tock shattering Kaby Lake processor as Moore’s Law falters". ArsTechnica.com. Jul 15, 2015. the switch to 10nm manufacturing has been delayed until the second half of 2017.
25. "Intel currently developing 14nm, aiming towards 5nm chips - CPU - News". HEXUS.net. 2012-05-15. Retrieved 2014-02-25.
26. "Intel’s Silvermont Architecture Revealed: Getting Serious About Mobile". AnandTech.
27. Hiroshige, Goto. "Intel Products for Tablets & SmartPhones" (PDF). 標準. Impress.
28. "Import Data and Price of anniedale".
29. "アウトオブオーダーと最新プロセスを採用する今後のAtom".
30. "Products (Formerly Braswell)". Intel® ARK (Product Specs). Retrieved 5 April 2016.
31. "venkata yelampalli".

External links

• Intel Automated Relational Knowledgebase