MASTAR MOSFET Model

The MASTAR (Model for Analog Simulation of subThreshold, saturation and weak Avalanche Regions)[1][2] is an analytical model of Metal-Oxide Semiconductor Field-Effect Transistors, developed using the voltage-doping transformation (VDT) technique [3] [4] [5] .[6] MASTAR offers good accuracy and continuity in current and its derivatives in all operation regimes of the MOSFET devices. The model has been successfully used in CAD/EDA simulation tools.[7]

The official ITRS definition of the acronymus MASTAR is Model for Assessment of CMOS Technologies And Roadmaps.[8] This software[9] [10] [11] is developed by STMicroelectronics and is freely distributed on ITRS organization web site.

References

  1. ↑ Skotnicki, T.; Merckel, G.; Denat, C. (1993), "A Model For Analog Simulation Of Subthreshold, Saturation And Weak Avalanche Regions In MOSFETs", International Workshop on VLSI Process and Device Modeling (May 14–15, 1993), pp. 146–147, doi:10.1109/VPAD.1993.724762, ISBN 0-7803-1338-0 |chapter= ignored (help)
  2. ↑ Skotnicki, T.; Denat, C.; Senn, P.; Merckel, G.; Hennion, B. (1994), "A new analog/digital CAD model for sub-halfmicron MOSFETs", Technical Digest., International Electron Devices Meeting (Dec. 11-14, 1994), pp. 165–168 Check date values in: |publication-date= (help)
  3. ↑ Skotnicki, T.; Marciniak, W. (1986), "A new approach to threshold voltage modelling of short-channel MOSFETS", Solid-State Electronics (November 1986) 29 (11), pp. 1115–1127, doi:10.1016/0038-1101(86)90054-7
  4. ↑ Skotnicki, T.; Merckel, G.; Pedron, T. (1988), "The voltage-doping transformation: a new approach to the modeling of MOSFET short-channel effects", IEEE Electron Device Letters (March 1988) 9 (3), pp. 109–112, doi:10.1109/55.2058
  5. ↑ Skotnicki, T.; Merckel, G.; Pedron, T. (1988), "A new punchthrough current model based on the voltage-doping transformation", IEEE Transactions on Electron Devices (Juin 1988) 35 (7), pp. 1076–1086, doi:10.1109/16.3367 Check date values in: |publication-date= (help)
  6. ↑ Skotnicki, T.; Merckel, G.; Pedron, T. (1989), "Analytical study of punchthrough in buried channel p-MOSFETs", IEEE Transactions on Electron Devices (Avril 1989) 36 (4), pp. 690–705, doi:10.1109/16.22474 Check date values in: |publication-date= (help)
  7. ↑ Modeling MOS Devices Using the MASTAR Model with UTMOST III
  8. ↑ ITRS Models, ITRS, retrieved 2013-03-15
  9. ↑ Skotnicki, Tomasz; Boeuf, Frédéric (2004), "Optimal scaling methodologies and transistor performance", Published in Book "High dielectric constant materials - VLSI MOSFET applications" Edited by Howard R. Huff and David Gilmer Springer series Microelectronics 16
  10. ↑ Skotnicki, Thomas; Hutchby, James A.; King, Tsu-Jae; Wong, H.-S. Philip; Boeuf, Frederic (2005), "The Road To The End Of Cmos Scaling", IEEE Circuits and Devices Magazine (Jan–Feb 2005) 21 (1), pp. 16–26, doi:10.1109/MCD.2005.1388765
  11. ↑ Skotnicki, Thomas; Fenouillet-Beranger, Claire; Gallon, Claire; Bœuf, Frederic; Monfray, Stephane; Payet, Fabrice; Pouydebasque, Arnaud; Szczap, Melanie; Farcy, Alexis; Arnaud, Franck; Clerc, Sylvain; Sellier, Manuel; Cathignol, Augustin; Schoellkopf, Jean-Pierre; Perea, Ernesto; Ferrant, Richard; Mingam, Hervé (2008), "Innovative materials devices and CMOS technologies for low-power mobile multimedia", IEEE Transaction on Electron Devices (January 2008) 55, pp. 96–130, doi:10.1109/TED.2007.911338

See also

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