Uncore

The uncore or system agent is a term used by Intel to describe the functions of a microprocessor that are not in the core, but which must be closely connected to the core to achieve high performance.[1] It has been called "system agent" since the release of Sandy Bridge Intel microarchitecture.[2] The core contains the components of the processor involved in executing instructions, including the ALU, FPU, L1 and L2 cache. Uncore functions include QPI controllers, L3 cache,[lower-alpha 1] snoop agent pipeline, on-die memory controller, and Thunderbolt controller.[3] Other bus controllers such as PCI Express[lower-alpha 2] and SPI are part of the chipset.[4]

The Intel uncore design stems from its origin as the Northbridge. The design of the Intel uncore reorganizes the functions critical to the core, making them physically closer to the core on-die, thereby reducing their access latency. Functions from the Northbridge which are less essential for the core, such as PCI Express[lower-alpha 2] or the Power Control Unit (PCU), are not integrated into the uncore – they remain as part of the chipset.[5]

Specifically, the microarchitecture of the Intel uncore is broken down into a number of modular units. The main uncore interface to the core is the so-called cache box (CBox), which interfaces with the Last Level Cache (LLC) and is responsible for managing cache coherency. Multiple internal and external QPI links are managed by Physical Layer units, referred to as PBox. Connections between the PBox, CBox, and one or more iMC's (MBox) are managed by System Config Controller (UBox) and a Router (RBox). [6]

Removal of serial bus controllers from the Intel uncore further enables increased performance by allowing the uncore clock (UCLK) to run at a base of 2.66 GHz, with upwards overclocking limits in excess of 3.44 GHz.[7] This increased clock rate allows the core to access critical functions (such as the iMC) with significantly less latency (typically reducing core access to DRAM by 10 ns or more).

Notes

  1. ↑ L3 cache is no longer considered part of the uncore since the release of Sandy Bridge microarchitecture.[2]
  2. 1 2 Some processors provide the PCI Express connectivity directly.

References

  1. ↑ "Ultrabook, SmartPhone, Laptop, Desktop, Server, & Embedded– Intel". Intel.com. Retrieved 2014-01-21.
  2. 1 2 Anand Lal Shimpi (September 14, 2010). "Intel's Sandy Bridge Architecture Exposed". AnandTech. Retrieved July 15, 2015.
  3. ↑ "Thunderbolt™ Technology for Developers". Intel.com. 2014-01-13. Retrieved 2014-01-21.
  4. ↑ "Nehalem: The Unwritten Chapters". AnandTech. Retrieved 2014-01-21.
  5. ↑ "IDF@Intel: A Time of New Beginnings: QuickPath, Power Control, Larrabee and SSDs". intel.com. Archived from the original on 2009-02-23. Retrieved 2014-01-30.
  6. ↑ "Intel(R) Xeon(R) Processor 7500 Series Uncore Programming Guide" (PDF). Retrieved 2014-01-30.
  7. ↑ Yus, Carlos (2011-01-27). "HighPerformanceSystems: Intel Sandy Bridge out of specification 4.0, 4.4 and 4.6 GHz. Updated – HighPerformanceSystems". Highperformancesystems.blogspot.com. Retrieved 2014-01-21.

External links


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