VerilogCSP

In integrated circuit design, VerilogCSP ^[1] is a set of macros added to Verilog HDL to support Communicating Sequential Processes (CSP) channel communications. These macros are intended to be used in designing digital asynchronous circuits. VerilogCSP also describes nonlinear pipelines and high-level channel timing properties, such as forward and backward latencies, minimum cycle time, and slack.

External links

• VerilogCSP Homepage

References

1. Saifhashemi, Arash; Peter Beerel. "High Level Modeling of Channel-Based Asynchronous Circuits Using Verilog". CPA 2005.