WARP (systolic array)

The Warp machines were a series of increasingly general-purpose systolic array processors, created by Carnegie Mellon University (CMU), in conjunction with industrial partners G.E., Honeywell and Intel, and funded by the U.S. Defense Advanced Research Projects Agency (DARPA).[1]

The Warp projects were started in 1984 by H. T. Kung at Carnegie Mellon University. The Warp projects yielded research results, publications and advancements in general purpose systolic hardware design, compiler design and systolic software algorithms. There were three distinct machine designs known as the WW-Warp (Wire Wrap Warp), PC-Warp (Printed Circuit Warp), and iWarp (integrated circuit Warp, conveniently also a play on the “i” for Intel).[2]

Each successive generation became increasingly general-purpose by increasing memory capacity and loosening the coupling between processors. Only the original WW-Warp forced a truly lock step sequencing of stages, which severely restricted its programmability but was in a sense the purest “systolic-array” design.

Warp machines were attached to Sun workstations (UNIX based). Software development for all models of Warp machines was done on Sun workstations.

A research compiler, for a language known as “W2,” targeted all three machines and was the only compiler for the WW-Warp and PC-Warp while it served as an early compiler during development of the iWarp.[3] The production compiler for iWarp was a C and Fortran compiler based on the AT&T pcc compiler for UNIX, ported under contract for Intel and then extensively modified and extend by Intel.[4]

The WW-Warp and PC-Warp machines were systolic array computers with a linear array of ten or more cells, each of which is a programmable processor capable of performing 10 million single precision floating-point operations per second (10 MFLOPS). A 10-cell machine had a peak performance of 100 MFLOPS. The iWarp machines doubled this performance, delivering 20 MFLOPS single precision and supporting double precision floating point at half the performance.[5]

A two cell prototype of WW-Warp was complete at Carnegie Mellon in June 1985. Two essentially identical ten-cell WW-Warp were produced in 1986, one by Honeywell and one by G.E., for use at Carnegie Mellon University. The system from G.E. was delivered in February 1986; the system from Honeywell was delivered in June 1986. The first of the significantly redesign production model, the PC-Warp, was delivered by G.E. in April 1987. About twenty production models of the PC-Warp were produced and sold by G.E. during 1987-1989.

The iWarp machines were based on a single-chip custom 700,000 transistor microprocessor, designed specifically for the Warp project, that utilized long-instruction-word (LIW) format instructions and tightly integrated communications with the computational processor. The standard iWarp machines configuration arranged iWarp nodes in a 2m x 2n torus. All iWarp machines included the “backedges” and, therefore, were tori.[6]

In 1986, Intel was selected, as a result of competitive bidding, to be the industrial partner for the integrated circuit implementation of Warp. The first iWarp system, a twelve node system, became operational in March 1990. After a number of stepping of the part, about 39 machines, consisting of ten or more C-Step iWarp chips running at 20MHz, were produced and sold by Intel in 1992 and 1993 to universities, government agencies and industrial research laboratories.[7]

Notes

  1. ↑ Thomas Gross and Monica Lam. 1998. Retrospective: a retrospective on the Warp machines. In 25 years of the international symposia on Computer architecture (selected papers) (ISCA '98), Gurindar S. Sohi (Ed.). ACM, New York, NY, USA, 45-47.
  2. ↑ Thomas Gross and David R. O'Hallaron. iWarp: anatomy of a parallel computing system, MIT Press, Cambridge, MA, 1998.
  3. ↑ Monica S. Lam. A Systolic Array Optimizing Compiler, Dordrecht, The Netherlands: Kluwer Academic Publishers, 1989.
  4. ↑ Ali-Reza Adl-Tabatabai, Thomas Gross, Guei-Yuan Lueh and James Reinders. Modeling Instruction-Level Parallelism for Software Pipelining. In Proceedings of the IFIP WG10.3 Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, Orlando, FL, pages 321-330.
  5. ↑ Intel Corp. iWarp Microprocessor (Part Number 318153), Hillsboro, Oregon, 1991. Technical Information, Order Number 281006.
  6. ↑ Shekhar Borkar, Robert Cohn, George Cox, Sha Gleason, and Thomas Gross. iWarp: an integrated solution of high-speed parallel computing, Proceedings of the 1988 ACM/IEEE conference on Supercomputing, p.330-339, November 12-17, 1988.
  7. ↑ Encyclopedia of Parallel Computing, Padua, David (Ed.), 2011, ISBN 978-0-387-09765-7

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