Wide-issue

A wide-issue architecture is a computer processor that issues more than one instruction per clock cycle.^[1] They can be considered in three broad types:

• Statically-scheduled superscalar architectures execute instructions in the order presented; the hardware logic determines which instructions are ready and safe to dispatch on each clock cycle.
• VLIW architectures rely on the programming software (compiler) to determine which instructions to dispatch on a given clock cycle.^[2]
• Dynamically-scheduled superscalar architectures execute instructions in an order that gives the same result as the order presented; the hardware logic determines which instructions are ready and safe to dispatch on each clock cycle.^[3]

See also

• Out-of-order execution
• Explicitly parallel instruction computing

References

1. "Scheduling for Superscalar & Multiple Issue Machines" (PDF).
2. "Wide Issue and Speculation".
3. Martin, Milo. "Superscalar" (PDF).