Write-once (cache coherence)

For other uses, see Write once (disambiguation).

In cache coherency protocol literature, Write-Once was the first write-invalidate protocol defined. It has the optimization of executing write-through on the first write and a write-back on all subsequent writes, reducing the overall bus traffic in consecutive writes to the computer memory. It was first described by James R. Goodman in (1983). Cache coherence protocols are an important issue in Symmetric multiprocessing systems, where each CPU maintains a cache of the memory.

States

In this protocol, each block in the local cache is in one of these four states:

These states have exactly the same meanings as the four states of the MESI protocol (they are simply listed in reverse order), but this is a simplified form of it that avoids the Read for Ownership operation. Instead, all invalidation is done by writes to main memory.

For any given pair of caches, the permitted states of a given cache line are as follows (abbreviated in the order above):

 I   V   R   D 
 I  Green tick Green tick Green tick Green tick
 V  Green tick Green tick Red X Red X
 R  Green tick Red X Red X Red X
 D  Green tick Red X Red X Red X

Transitions

The protocol follows some transition rules for each event:

Write-Once Transition Diagram
The "WM" transition from the Invalid state is erroneous; the write must be written through to memory and so leaves the line in the Reserved state.

This is a variant of the MESI protocol, but there is no explicit read-for-ownership or broadcast invalidate operation to bring a line into cache in the Exclusive state without performing a main memory write. Instead, the first write to a Valid (a.k.a. Shared) cache line performs a write through to memory, which implicitly invalidates other caches. After that, the line is in the Reserved (Exclusive) state, and further writes can be done without reference to main memory, leaving the cache line in the Dirty (Modified) state.

References

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