XCore XS1-AnA
 | |
| Produced | 2013 |
|---|---|
| Max. CPU clock rate | to 500 MHz |
| Instruction set | XCore XS1 |
| Cores | 1 or 2 |
| Package(s) | |
The 'XS1-AnA[1][2] is a family of processors designed by XMOS. It is based on a 32-bit architecture, that runs up to eight concurrent threads, with built-in analog-to-digital converters (ADC), oscillator, and power supplies. It will be available from autumn 2013 running at 500 MHz. Each thread can run at up to 125 MHz.
Description
The XS1-AnA comprises a single or dual tile processor, each with a switch, digital I/O ports, and set of analogue input channels. The execution core has a data path, a memory, and register banks for eight threads. The switches of two or more XS1-AnA, xCORE-UnA and Xcore XS1-L processors can be connected using one or more links, whereupon threads on all of the tiles can communicate with each other by exchanging messages through the switches. The XCore XS1 instruction set architecture supports 12 general purpose registers per thread. A standard 3-operand instruction set is used for programming the thread.
Input and output
The processor can perform input and output directly from the instruction set using IN and OUT instructions. Complex interfaces are designed by programming a sequence of IN and OUT instructions. The XCore XS1 instruction set architecture has a built-in scheduler that deschedules threads that wait for an IN or an OUT to complete until the operation completes. This enables event-driven programming.
The IN and OUT instructions operate on binary data. This may be a bit pattern that was sampled on a set of general purpose digital I/O pins, or it may be reading data from some physical layer (PHY). This can be a built-in analog-to-digital converter (ADC), or an external PHY.
References
- ↑ "XCore XS1-A8A-64-FB96 datasheet". XMOS web site. Retrieved 2013-07-01.
- ↑ "XCore XS1-A16A-128-FB217 datasheet". XMOS web site. Retrieved 2013-07-01.