SSL acceleration

PCI-X Crypto Accelerator

SSL acceleration is a method of offloading processor-intensive public-key encryption for Transport Layer Security (TLS) and its predecessor Secure Sockets Layer (SSL) to a hardware accelerator.

Typically this means having a separate card that plugs into a PCI slot in a computer that contains one or more co-processors able to handle much of the SSL processing.

SSL accelerators may use off the shelf CPUs, but most use custom ASICs and RISC chips to do most of the difficult computational work.

How it works

The most computationally expensive part of an SSL session is the SSL handshake, where the SSL server (usually an SSL webserver) and the SSL client (usually a web browser) agree on a number of parameters that establish the security of the connection.

Part of the role of the SSL handshake is to agree on session keys (symmetric keys, used for the duration of a given session), but the encryption and signature of the SSL handshake messages itself is done using asymmetric keys (contained in the certificates), which requires more computational power than the symmetric cryptography used for the encryption/decryption of the session data.

Typically a hardware SSL accelerator will offload processing of the SSL handshake while leaving it to the server software to process the less intense symmetric cryptography of the actual SSL data exchange, but some accelerators handle all SSL operations and terminate the SSL connection, thus leaving the server seeing only unencrypted connections.

Central processor support

Modern x86 CPUs support Advanced Encryption Standard (AES) encoding and decoding in hardware, using the AES instruction set proposed by Intel in March 2008.

Allwinner Technology provides a hardware cryptographic accelerator in its A10, A20, A30 and A80 ARM system-on-chip series. The accelerator provides the RSA public-key algorithm, several widely used symmetric-key_algorithms, cryptographic hash functions, and a cryptographically secure pseudo-random number generator.^[1]

TLS & SSL

TLS 1 was first defined in RFC 2246 in January 1999 as an upgrade to SSL Version 3. Because TLS is essentially an updated form of SSL, TLS session acceleration is essentially the same thing as SSL acceleration.

As stated in the RFC, "the differences between this protocol and SSL 3 are not dramatic, but they are significant enough that TLS 1 and SSL 3 do not interoperate." TLS 1 does include a means by which a TLS implementation can downgrade the connection to SSL 3.

The current version of TLS (1.2) was defined in RFC 5246 in August 2008. It is based on the earlier TLS 1.1 specification.

Vendors

A10 Networks Barracuda Networks Array Networks CAI Networks Cavium Networks Cisco Systems

Citrix Systems Cotendo Coyote point systems Crescendo Networks Exinda F5 Networks

Foundry Networks Forum Systems Freescale Semiconductor Hifn IBM Intel Interface Masters Technologies jetNEXUS Juniper Networks

KEMP Technologies Nortel Networks PIOLINK Radware Riverbed Technology Strangeloop Networks Sun Microsystems Network Box

See also

Related technologies

• Coprocessor
• Public-key cryptography
• TLS
• Stunnel

References

1. [PATCH v5] crypto: Add Allwinner Security System crypto accelerator on Linux ARM kernel mailing list

External links

• Information Site Dedicated to SSL Acceleration
• SSL Acceleration and Offloading: What Are the Security Implications?