Vortex86
The Vortex86 is a computing system-on-a-chip (SoC) based on a core compatible with the x86 microprocessor family. It formerly belonged to SiS, which got the basic design from Rise Technology,[1] and was sold to the Taiwanese DM&P Electronics.[2]
Versions
Vortex86 original
SiS55x/Rise mP6 or simply Vortex86) – Developed by SiS, three integer and MMX pipelines, branch prediction [3]
Vortex86SX
300 MHz, 16 KB Data + 16 KB Instruction L1 cache, no FPU, no L2 cache. Can use both SD and DDR2 RAM [4]
Vortex86DX
600 MHz to 1 GHz (2.02 W @ 800 MHz [5]), 16 KB Data + 16 KB Instruction L1 cache, FPU, 512 KB L2 cache, 6-staged pipeline. Can address up to 1 GiB DDR2 RAM[6][7] The PDX-600 is a version of the Vortex86DX that only differs in the number of RS-232 ports (3 instead of 5) and has no I²C and servo controllers, thus targeting more the embedded than the industrial market. Netbooks similar to the Belco 450R use this chip.[8]
Vortex86MX
1 GHz, the CPU core itself hardly differs from the Vortex86DX, but according to several sites, the processor does appear to have implemented SIMD multi-media instructions (MMX).[9][10][11] This version drops conformance to ISA and integrates a GPU and a HD Audio controller, it also integrates a UDMA/100 IDE controller. The consumer grade version is known as the PMX-1000.[12] Current models of the Gecko Edubook use the Xcore86, a rebadge of the Vortex86MX.[12]
Vortex86MX+
This has a 32KB write through 2-way L1 cache, 512KB write through/write back 2-way L2 cache, PCI rev. 2.1 32-bit bus interface at 33 MHz, DDR2, ROM controller, IPC (Internal Peripheral Controllers with DMA and interrupt timer/counter included), Fast Ethernet, FIFO UART, USB2.0 Host and ATA controller.
The package is a single 720-pin BGA package.
Vortex86DX2
This has a 32KB write through 2-way L1 cache, 512KB write through/write back 2-way L2 cache, PCI rev. 2.1 32-bit bus interface at 33 MHz, DDR2, ROM controller, IPC (Internal Peripheral Controllers with DMA and interrupt timer/counter included), VGA, Fast Ethernet, FIFO UART, USB2.0 Host and ATA controller.
The package is a single 720-pin BGA package.
Vortex86EX
This has a 32KB write through 2-way L1 cache, 128KB write through/write back 2-way L2 cache, PCI-e bus interface, 300 MHz DDR3, ROM controller, IPC (Internal Peripheral Controllers with DMA and interrupt timer/counter included), Fast Ethernet, FIFO UART, USB2.0 Host and ATA controller.
The package is a single 288-pin TFBGA-package.
Vortex86DX3
this has a 8 way 32K I-Cache, 8-way 32K D-Cache, 4-way 512KB L2 Cache with write through or write back policy, 300 MHZ DDR3 ( DDR3 ram size up to 2Gb ( possibly 4GB)), PCI-e bus interface, fast ethernet, FIFO UART, USB2.0 Host , ATA controller that has IDE controller, PATA 100(2x HDD) or 2x SD at Primary Channel and SATA 1.5Gb/s (1 Port) at Secondary Channel
The package is a single 720-pin BGA-package
CPU
The CPU implements the i586 architecture, but the early versions Vortex86 original and Vortex86SX do not have a floating point unit (FPU). Any code that runs on an i486SX CPU without a 487 will run on Vortex86, as will any code that runs on i586 but does not use floating point instructions. Any i586 code will run on Vortex86DX and later. Some Linux kernels (by build-time option) emulate the FPU on any CPU that is missing one, so that even a program that uses floating point instructions, if it runs under Linux, works on any Vortex86 CPU, albeit slowly.
Code intended for i686 may fail because the CPU lacks a Conditional Move (CMOV) instruction. This is an instruction that combines the effect of a conditional branch and a move instruction. Compilers asked to optimize code for a more advanced CPU (for example the GNU Compiler with its -march=i686 option) generate code that uses CMOV. Linux systems intended to run on i686 are generally not runnable on Vortex86 because the GNU C Library, when built for i686, uses a CMOV instruction in its assembly language strcmp function, which its dynamic loader (ld.so) uses. Hence, no program that uses shared libraries can even start up.
Technically, CMOV is optional in the i686 architecture. But Intel's i686 product, the Pentium Pro, had it, and consequently things that generate code typically consider CMOV to be available when you ask them to generate code for i686.
Here is what the Linux kernel reports (via /proc/cpuinfo) about the properties of a Vortex86 original CPU. Note that it says an FPU is available, though the CPU does not have one. This reflects the fact that the Linux kernel emulates the FPU.
processor : 0 vendor_id : SiS SiS SiS cpu family : 5 model : 0 model name : 05/00 stepping : 5 cpu MHz : 199.978 fdiv_bug : no hlt_bug : no f00f_bug : no coma_bug : no fpu : yes fpu_exception : yes cpuid level : 1 wp : yes flags : fpu tsc cx8 mmx up bogomips : 399.95 clflush size : 32 cache_alignment : 32 address sizes : 32 bits physical, 32 bits virtual power management:
Compatible Components
DM&P provides an embedded Linux distribution customized to use the SoCs features.[14]
History
Before adopting the Vortex86 series, DM&P manufactured the M6117D, an Intel 386SX compatible, 25–40 MHz SoC.[15][16]
See also
External links
References
- ↑ Cebit 2007: x86 Minisystem mit Vortex86SX (german)
- ↑ Vortex86 Envision Embedded Design with Windows Embedded Technologies
- ↑ Vortex86 Data Sheet
- ↑ Vortex86SX Data Sheet
- ↑ Vortex86DX overview
- ↑ Vortex86DX documentation
- ↑ Vortex86DX Data Sheet
- ↑ engadget - "The world's cheapest laptop"
- ↑ Thomas, Alexander (November 2012). "BTplug Review". Dr. Lex' Site. Retrieved 2012-02-13.
- ↑ Kauler, Barry (2010-01-16). "Xcore86 CPU in Gecko Edubook". Barry's Blog. Retrieved 2015-02-13. — See blog comments for more information.
- ↑ LoneRifle (2010-01-22). "CPU Features". Flickr. Retrieved 2015-02-13.
- 1 2 Angel, Jonathan (2008-12-11). "X86 system-on-chip adds VGA graphics". LinuxForDevices. Archived from the original on 2012-09-12. Retrieved 2009-12-11.
- ↑ http://www.cnx-software.com/2015/04/09/vortex86dx3-is-a-new-x86-soc-for-embedded-systems/
- ↑ X-Linux
- ↑ M6117D Data Sheet
- ↑ M6117D overview