PowerPC e200

The PowerPC e200 is a family of 32-bit Power Architecture microprocessor cores developed by Freescale for primary use in automotive and industrial control systems. The cores are designed to form the CPU part in system-on-a-chip (SoC) designs with speed ranging up to 600 MHz, thus making them ideal for embedded applications.

The e200 core is developed from the MPC5xx family processors, which in turn is derived from the MPC8xx core in the PowerQUICC SoC processors. e200 adheres to the Power ISA v.2.03 as well as the previous Book E specification. All e200 core based microprocessors are named in the MPC55xx and MPC56xx/JPC56x scheme, not to be confused with the MPC52xx processors which is based on the PowerPC e300 core.

In April 2007 Freescale and IPextreme opened up the e200 cores for licensing to other manufacturers.

Continental AG and Freescale are developing SPACE, a tri-core e200 based processor designed for electronic brake systems in cars.

STMicroelectronics and Freescale have jointly developed microcontrollers for automotive applications based on e200 in the MPC56xx/SPC56x family.

Cores

The e200 family consists of six cores, from simple low-end to complex high-end in nature.

e200z0

The simplest core, e200z0 features an in order, four stage pipeline. It has no MMU, no cache, and no FPU. It uses the variable bit length (VLE) part of the Power ISA, which uses 16-bit versions of the otherwise standard 32-bit PowerPC Book E ISA, thus reducing code footprint by up to 30%. It has a single 32-bit AMBA 2.0v6 bus interface. The load/store unit is pipelined, has a 1-cycle load latency and supports throughput of one load or store operation per cycle.

The e200z0 is used in the MPC5510 as an optional co-processor alongside an e200z1 core, making that chip a multicore processor. e200z0 is available as co-processors to other e200 based processors as well as very low end stand alone processors.

e200z1

The e200z1 has a four-stage, single-issue pipeline with a branch prediction unit and an 8 entry MMU, no cache and no FPU. It can use the complete 32-bit PowerPC ISA as well as the VLE instructions. It uses a dual 32-bit AMBA 2.0v6 bus interface. The load/store unit is pipelined, has a 1-cycle load latency and supports throughput of one load or store operation per cycle.

e200z3

The e200z3 has a four-stage, single-issue pipeline with a branch prediction unit, a 16 entry MMU and a SIMD capable FPU. It has no cache. It can use the complete 32-bit PowerPC ISA as well as the VLE instructions. It uses a dual 64-bit AMBA 2.0v6 bus interface. The load/store unit is pipelined, has a 1-cycle load latency and supports throughput of one load or store operation per cycle.

e200z4

The e200z4 has a five-stage, dual-issue pipeline with a branch prediction unit, a 16 entry MMU, signal processing extension (SPE), a SIMD capable single precision FPU and a 4 Kilobyte 2/4-way set associative instruction L1 cache (Pseudo round-robin replacement algorithm). It has no data cache. It can use the complete 32-bit PowerPC ISA as well as the VLE instructions. It uses a dual 64-bit bus AMBA 2.0v6 interface. The load/store unit is pipelined, has a 2-cycle load latency and supports throughput of one load or store operation per cycle.

e200z6

The e200z6 has a seven-stage, single-issue pipeline with a branch prediction unit, a 32 entry MMU, signal processing extensions (SPE), a SIMD capable single-precision FPU and an 8-way set associative 32 KiB unified data/instruction L1 cache. It can use the complete 32-bit PowerPC ISA as well as the VLE instructions. It uses a single 64-bit bus AMBA 2.0v6 interface. The load/store unit is pipelined, has a 3-cycle load latency and supports throughput of one load or store operation per cycle.

e200z7

The e200z7 has a ten-stage, dual-issue pipeline with a branch prediction unit, a 32 entry MMU, a SIMD capable single-precision FPU and 16-KB, 4 way set-associative Harvard instruction and data L1 caches. It can use the complete 32-bit PowerPC ISA as well as the VLE instructions. It uses a 32-bit bus AMBA 2.0v6 interface for the address bus, and a 64-bit data bus (plus attributes and control on each bus). The load/store unit is pipelined, has a 3-cycle load latency and supports throughput of one load or store operation per cycle.

See also

• PowerPC 5000
• PowerPC
• Power Architecture

References

• Freescale's MPC55xx page
• ST's SPC5 page
• IPextremes e200 licensing page
• Freescale’s e200 Core Family, Overview and Licensing Model, White paper
• Multi-Core Design: Key Challenges and Opportunities – Power.org
• Halfhill, Tom R. (2 April 2007). "Freescale Licenses Power Cores". Microprocessor Report.