Verilog-to-Routing

Verilog-to-Routing (VTR) is an open source CAD tool for FPGA devices.[1][2] The tool's main purpose is to map a given circuit described in Verilog, which is a hardware design language, on a given FPGA architecture for research and development purposes. The VTR project is a collaboration between the University of New Brunswick, the University of California, Berkeley and the University of Toronto. Furthermore, Altera and Texas Instruments are also contributors. The latest edition is VTR 7.0, which was made available in 2014.

VTR Flow

VTR utilizes a flow of three component applications: First, ODIN II compiles the Verilog code to a circuit in Berkeley Logic Interchange Format (BLIF), which is a human-readable graph representation of the circuit.[3] Second, ABC optimizes the BLIF circuit produced by ODIN II. Third, VPR packs, places and routes the optimized circuit on the given FPGA architecture.

ODIN II

ODIN II is the compiler of the VTR flow. It transforms a given Verilog code to a BLIF circuit, performs code and circuit optimizations, visualizes circuits,[4] and performs partial mapping of logic to available hard blocks of the given architecture. Also, it can simulate the execution of circuits both for validation as well as power, performance and heat analysis. ODIN II is maintained by the University of New Brunswick.[5]

ABC

ABC optimizes BLIF circuits by performing logical reductions and Karnaugh map optimizations. ABC is maintained by the University of California, Berkeley.[6]

VPR

Versatile Placement and Routing (VPR) is the final component of VTR. Its input is a BLIF circuit, which it packs, places and routes on an input FPGA architecture. First, neighboring and related logic elements of the circuit are grouped together to larger pieces of logic. Then, these larger logic modules as well as hard blocks are mapped to the available hardware logic blocks of the FPGA. Finally, the routing of the FPGA is calculated such that the logic blocks are properly connected. VPR is maintained by the University of Toronto.[7]

See also

References

  1. ↑ "VTR 7.0: Next Generation Architecture and CAD System for FPGAs". ACM Trans. Reconfigurable Technol. Syst. 7: 6:1–6:30. 2014.
  2. ↑ "The VTR project: architecture and CAD for FPGAs from verilog to routing". Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays. 2012.
  3. ↑ "Berkeley logic interchange format (BLIF)". Oct Tools Distribution 2: 197–247. 1992.
  4. ↑ "Visualization support for FPGA architecture exploration". 23rd IEEE International Symposium on Rapid System Prototyping (RSP): 128–134. 2012.
  5. ↑ "Odin II-an open-source verilog HDL synthesis tool for CAD research". 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM): 149–156. 2010.
  6. ↑ "A system for sequential synthesis and verification". Berkeley A. B. C. 2009.
  7. ↑ "VPR: A new packing, placement and routing tool for FPGA research". Field-Programmable Logic and Applications. Springer Berlin Heidelberg. 1997.

External links

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