Saraju Mohanty

Saraju Mohanty

Prof. Saraju P. Mohanty in 2012
Born Odisha, India
Residence Denton, Texas, USA
Nationality United States USA
Alma mater University of South Florida (USF), Tampa
Indian Institute of Science (IISc), Bangalore
Orissa University of Agriculture and Technology (OUAT), Bhubaneswar
Occupation Professor, Author, Scientist, Engineer, Computer engineer
Faculty University of North Texas
Known for Mixed-Signal Systems, Nanoelectronics Systems, Metamodeling, Design for X, High-level synthesis (HLS), Hardware-assisted Digital watermarking
Notable work Nanoelectronic Mixed-Signal System Design, McGraw-Hill, 2015, ISBN 978-0071825719
Spouse(s) Dr. Uma Choppali
Honors

Chair, Technical Committee on VLSI (TCVLSI), IEEE Computer Society (IEEE-CS).

2016 PROSE Award for best Textbook in Physical Sciences & Mathematics from the AAP.
Website www.smohanty.org

Saraju Mohanty is a Professor and Associate Chair of the Department of Computer Science and Engineering (CSE), and the Director of the NanoSystem Design Laboratory (NSDL), at the University of North Texas (UNT) in Denton, Texas.[1][2] Professor Mohanty is a researcher in the areas of "Low-Power High-Performance Nanoelectronics Systems" and "hardware-assisted Digital watermarking".[3] He has made significant research contributions to Analogue electronics and Mixed-signal integrated circuit Computer-aided design (CAD) and Electronic design automation (EDA), nanoelectronic technology based High-level synthesis (HLS), and hardware-assisted Digital watermarking. He is currently the Chair of the Technical Committee on Very Large Scale Integration or Technical Committee on VLSI (TCVLSI), IEEE Computer Society (IEEE-CS) since September 2014.[4][5] He is a senior member of both the Institute of Electrical and Electronics Engineers (IEEE) and the Association for Computing Machinery (ACM). He is an inventor of 4 US patents in the areas of his research. Professor Mohanty has published 200 papers and 3 books in the areas of his research.[6][7][8] The scientific articles of Prof. Mohanty are significant contributions to the engineering discipline, scientific community, and society.[9][10][11] He received 2016 PROSE Award for best Textbook in Physical Sciences & Mathematics from the AAP for his book titled "Nanoelectronic Mixed-Signal System Design." His research contributions are well-cited by researchers in different parts of the globe as evident from his Google Scholar metrics.[12] His research has been well-funded by various agencies such as the NSF, the SRC, and the Air Force.[13][14] Professor Mohanty is a very popular professor among students as a professor who cares for them and offers quality materials in a simplified manner.[15]

Notable Scientific Contributions

Contributions to Analog Electronics and Mixed-Signal Circuits

Saraju Mohanty has introduced several novel approaches for ultra-fast design space exploration and optimization of nanoelectronic integrated circuits which can result in energy-efficient, robust, and nanoscale variation-tolerant Analog electronics circuits as well as Mixed-signal integrated circuits. The key feature of these ultra-fast design flows is the need for only two manual layout (or physical design) iterations which saves significant design effort. These ultra-fast design flows rely on accurate metamodels of the analog and mixed-signal circuit components. His research significantly advances the state-of-the art in Design for Excellence (DfX) or Design for X, such as Design for Variability (DfV) and Design for Cost (DfC).[16] The metamodel assisted ultra-fast design optimization flows can perform layout optimization of the components of analog/mixed-signal System on a chip (AMS-SoC) with very minimal design effort. These techniques can lead to over 1,000X speedups. As a specific example, nanoelectronics based phase-locked loop (PLL) which would typically need several days of design cycle for analog simulation with fully modeled parasitics can be optimally designed in less than a day .[17] [18] These ultra-fast and accurate methodologies lead to robust and low-cost consumer electronics such as smart mobile phones, making them cheaper and available to larger segments of the population.

Contributions to High-Level Synthesis

Saraju Mohanty is one of the key contributors to nanoscale CMOS or nanoelectronic technology based High-level synthesis (HLS) or architecture-level synthesis.[19][20][21] His nanoelectronic-based High-level synthesis techniques addresses the issue of process variations, the primary issue of nanoelectronic technology, during the high-level synthesis itself before the digital design moves to the detailed and lower levels of design abstractions, such as logic-level or transistor-level.[22] This is a significant effort saver for digital design engineers as the digital design is statistically optimized at the higher-level of abstraction. His HLS techniques produce Register-transfer level descriptions which not only meet traditional specifications, but are also robust against nanoscale process-variations. His HLS techniques are also the first ones to address transient power dissipation or power fluctuation during high-level synthesis, thus distinguishing power-aware design and battery-aware design at the higher levels of design abstractions. This is a very important contribution for digital circuits targeted towards portable AMS-SoCs. Additionally, his research projects in the area of security aware HLS, is one of the upcoming fields in the area of digital integrated circuits and VLSI-CAD. Security aware HLS is an effort to generate datapath designs during HLS that consider security at behavioral level. This research area considers reliability as design specification from the highest design abstraction level. Security aware HLS is important for mission critical applications such as in military/army where hardware security is crucial for trustworthy hardware design.

Contributions to Digital Watermarking

Saraju Mohanty is a pioneer in hardware-assisted Digital watermarking for real-time copy protection and digital rights management (DRM). He has invented the concept of Secure Digital Camera (SDC) for real-time Digital rights management (DRM) at the source end of the multimedia content.[23][24] [25] The SDC has quite diverse applications where still image or video digital cameras are needed, such as secure Digital Video Broadcasting, secure Video Surveillance, electronic passport, and identity card processing. The secure digital camera (SDC) has been well-adopted by various researchers worldwide. In the process it has led to diverse implementations in various platforms by many researchers worldwide.[26][27] [28] Professor Mohanty is the designer of the earliest and unique energy-efficient digital watermarking chips.[29] An earliest watermarking chip designed by him can perform invisible digital watermarking at the spatial domain and has capability of both robust and fragile watermarking depending on the choice of the user.[30] A unique digital watermarking chip designed by Professor Mohanty that can perform both visible watermarking and invisible watermarking is the lowest power consuming watermarking chip available at present.

Professional Leadership

Editorial Board

Guest Editor

Conference Steering Committee Member

Conference General or Program Chair

Notable Talks

Professional Membership

Honors and Awards

Patents

Saraju Mohanty is an inventor of 4 US patents which have wide applications in Digital watermarking, Digital rights management (DRM), and Mixed-signal integrated circuit design:[71][72][73]

Saraju Mohanty with his best seller nanoelectronic mixed-signal system design book published in 2015 by McGraw-Hill Education.
Saraju Mohanty with his best seller nanoelectronic mixed-signal system design book published in 2015 by McGraw-Hill Education.

Books

Saraju Mohanty has authored or edited 6 books which are widely used as reference text books:

Notable Articles for Advancement of Science and Engineering

  • Incorporating Manufacturing Process Variation Awareness in Fast Design Optimization of Nanoscale CMOS VCOs, IEEE Transactions on Semiconductor Manufacturing, February 2014.
  • Fast Layout Optimization through Simple Kriging Metamodeling: A Sense Amplifier Case Study, IEEE Transactions on Very Large Scale Integration Systems, April 2014.
  • Variability-Aware Architecture Level Optimization Techniques for Robust Nanoscale Chip Design, Elsevier International Journal on Computers and Electrical Engineering, January 2014.
  • ULS: A Dual-Vth/High-κ Nano-CMOS Universal Level Shifter for System-Level Power Management, ACM Journal on Emerging Technologies in Computing Systems, June 2010.
  • IntellBatt: Toward A Smarter Battery, IEEE Computer, March 2010.
  • Design of Parasitic and Process Variation Aware RF Circuits: A Nano-CMOS VCO Case Study, IEEE Transactions on Very Large Scale Integration Systems, September 2009.
  • A Secure Digital Camera Architecture for Integrated Real-Time Digital Rights Management, Elsevier Journal of Systems Architecture, October–December 2009.
  • Single Ended 6T SRAM with Isolated Read-Port for Low-Power Embedded Systems, 12th IEEE International Conference on Design Automation and Test in Europe, 2009.
  • Hardware Assisted Watermarking for Multimedia, Elsevier International Journal on Computers and Electrical Engineering, March 2009.
  • Invisible Watermarking Based on Creation and Robust Insertion-Extraction of Image Adaptive Watermarks, ACM Transactions on Multimedia Computing, Communications, and Applications, November 2008.
  • IntellBatt: Towards Smarter Battery Design, 45th ACM/IEEE Design Automation Conference, 2008.
  • VLSI Architecture and Chip for Combined Invisible Robust and Fragile Watermarking, IET Computers & Digital Techniques, September 2007.
  • A Dual Voltage-Frequency VLSI Chip for Image Watermarking in DCT Domain, IEEE Transactions on Circuits and Systems II, May 2006.
  • Physical-Aware Simulated Annealing Optimization of Gate Leakage in Nanoscale Datapath Circuits, 9th IEEE International Conference on Design Automation and Test in Europe, 2006.
  • A VLSI Architecture for Visible Watermarking in a Secure Still Digital Camera (S2DC) Design, IEEE Transactions on Very Large Scale Integration Systems, August 2005.
  • A Framework for Energy and Transient Power Reduction during Behavioral Synthesis, IEEE Transactions on Very Large Scale Integration Systems, June 2004.
  • VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design, 17th International Conference on VLSI Design, 2004.
  • VLSI Implementation of Invisible Digital Watermarking Algorithms Towards the Development of a Secure JPEG Encoder, the IEEE Workshop on Signal Processing System, 2003
  • A DCT Domain Visible Watermarking Technique for Images, 1st IEEE International Conference on Multimedia and Expo, 2000.
  • A Dual Watermarking Technique for Images, 7th ACM International Multimedia Conference, 1999.

Gallery

Doctoral Dissertations Supervised

Education

Professor Mohanty earned a Ph.D. in Computer engineering from the University of South Florida (USF) in 2003. His Ph.D. mentor at the University of South Florida was Professor N. Ranganathan (IEEE Fellow and AAAS Fellow).[84]

He received master's degree in Engineering in Systems Science and Automation (SSA) from the Indian Institute of Science (IISc), Bangalore, India in 1999. His master's thesis mentors at the Indian Institute of Science (IISc), Bangalore were Professor K. R. Ramakrishnan[85] and Professor Mohan S. Kankanhalli[86] (IEEE Fellow). He carried out his Master's thesis work at the Multimedia Systems Laboratory (MMSL) of the Supercomputer Education and Research Centre (SERC) at Indian Institute of Science. During that time the MMSL at SERC used to be directed by Padma Shri award winner Professor Narayanaswamy Balakrishnan[87] who was also the Associate Director of the Indian Institute of Science for several years.

He received his bachelor's degree (with Honors) in Electrical Engineering (EE) from the College of Engineering and Technology, Bhubaneswar, Orissa University of Agriculture and Technology (OUAT), Bhubaneswar, India in 1995. The College of Engineering and Technology, Bhubaneswar is an institute owned by the Government of Odisha located in the capital city of Bhubaneswar which only admits top-ranked holders of the state Engineering Entrance Examination. He received a number of scholarships throughout his undergraduate and graduate studies.

He completed a 10+2 Science degree from the Rajdhani College, Bhubaneswar in 1990. His high school education from the Badagada Government High School, Bhubaneswar completed in 1988. He was a quite active and recognized member of The Bharat Scouts and Guides.

Personal life

Professor Mohanty was born in Lodhachua, Ranpur, in the state of Odisha, India near the capital city of Bhubaneswar. He lived in Bhubaneswar until he completed his undergraduate education from College of Engineering and Technology, Bhubaneswar. In 1997, he moved to Bangalore for his Masters studies at Indian Institute of Science (IISc) Bangalore. After completing the Masters education, he moved to USA for his doctoral education. In 2003, he completed his Ph.D. It is during while doing his doctoral studies that he met his wife Dr. Uma Choppali. Dr. Uma Choppali had her Masters in Physics from the Indian Institute of Technology Bombay, India. She was enrolled in Ph.D. (Physics) at the University of South Florida at Tampa, Florida, when they met. They got married in 2003 at Tampa, Florida. Dr. Uma Choppali completed her Ph.D. in Materials Science and Engineering from the University of North Texas at Denton.

References

  1. ↑ The University of North Texas, Dept. of Computer Science and Engineering, NanoSystem Design Laboratory, http://nsdl.cse.unt.edu/
  2. ↑ The University of North Texas, Dept. of Computer Science and Engineering, http://www.cse.unt.edu/site/node/91
  3. ↑ Research Interests, Prof. Saraju Mohanty, http://www.cse.unt.edu/~smohanty/Research.html
  4. ↑ Dr. Saraju Mohanty Serves as the Chair of the Technical Committee on Very Large Scale Integration (TCVLSI), https://facultysuccess.unt.edu/dr-saraju-mohanty-serves-chair-technical-committee-very-large-scale-integration-tcvlsi
  5. ↑ Technical Committee on VLSI, http://www.computer.org/portal/web/tandc/tcvlsi
  6. ↑ ResearchGate - Saraju Mohanty, http://www.researchgate.net/profile/Saraju_Mohanty
  7. ↑ Google Scholar List - Saraju Mohanty, https://scholar.google.com/scholar?hl=en&q=saraju+mohanty
  8. ↑ DBLP - Saraju Mohanty, http://dblp.uni-trier.de/pers/hd/m/Mohanty:Saraju_P=.html
  9. ↑ Interviews: Energy Efficient Buildings & Communities Workshop, University of Tartu, Estonia, http://www.uttv.ee/naita?id=17227&keel=eng
  10. ↑ Less time on the charger, http://www.unt.edu/features/mohanty/index.htm
  11. ↑ US Department of Energy, E-print Network, Computer Technologies and Information Sciences, Preprints Provided by Individual Scientists, http://www.osti.gov/eprints/pathways/computertechM.shtml
  12. ↑ Google Scholar Citation - Saraju P. Mohanty, https://scholar.google.com/citations?user=G0uvNwsAAAAJ&hl=en
  13. ↑ At one-billionth of a meter, scientists create on the cutting edge, UNT Research Magazine, Volume 20, 2011, http://www.unt.edu/untresearch/2010-2011/advancing-nanotechnology.htm
  14. ↑ UNT researcher works to make energy-efficient chips, August 20, 2009, https://news.unt.edu/news-releases/unt-researcher-works-make-energy-efficient-chips
  15. ↑ Rate my Professors, Saraju Mohanty, Professor in the Computer Science department, University of North Texas, Denton, TX, http://www.ratemyprofessors.com/ShowRatings.jsp?tid=1664572
  16. ↑ DFX for Nanoelectronic Embedded Systems, Keynote Address at First IEEE Sponsored International Conference on Control, Automation, Robotics and Embedded System, CARE-2013, http://care.iiitdmj.ac.in/Keynote_Speakers.html.
  17. ↑ S. P. Mohanty and E. Kougianos, "Polynomial Metamodel Based Fast Optimization of Nano-CMOS Oscillator Circuits", Analog Integrated Circuits and Signal Processing Journal, Vol. 79, Issue 3, June 2014, pp. 437-453.
  18. ↑ S. P. Mohanty and E. Kougianos, "Incorporating Manufacturing Process Variation Awareness in Fast Design Optimization of Nanoscale CMOS VCOs", IEEE Transactions on Semiconductor Manufacturing, Vol. 27, Issue 1, February 2014, pp. 22--31.
  19. ↑ Saraju Mohanty and Elias Kougianos, "Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis", in Proceedings of the 20th International Conference on VLSI Design, pp. 577-582, 2007.
  20. ↑ S. P. Mohanty, M. Gomathisankaran, and E. Kougianos, "Variability-Aware Architecture Level Optimization Techniques for Robust Nanoscale Chip Design", Elsevier Computers and Electrical Engineering Journal, Vol. 40, Issue 1, January 2014, pp. 168--193.
  21. ↑ Y. Chen, Y. Wang, A. Takach, Y. Xie. "Parametric Yield Driven Resource Binding in High-Level Synthesis with Multi-Vth Vdd Library and Device Sizing", Journal of Electrical and Computer Engineering, Volume 2012, Article ID 105250, 14 pages, 2012.
  22. ↑ "Unified Challenges in Nano-CMOS High-Level Synthesis", Invited Talk, 22nd IEEE International Conference on VLSI Design, 2009.
  23. ↑ Secure digital camera#Secure digital camera
  24. ↑ Saraju Mohanty, "A Secure Digital Camera Architecture for Integrated Real-Time Digital Rights Management", Elsevier Journal of Systems Architecture, Vol. 55, Issues 10-12, Oct-Dec 2009, pp. 468-480.
  25. ↑ S. P. Mohanty, O. B. Adamo, and E. Kougianos, "VLSI Architecture of an Invisible Watermarking Unit for a Biometric-Based Security System in a Digital Camera", in Proceedings of the 25th IEEE International Conference on Consumer Electronics, pp. 485-486, 2007.
  26. ↑ Thomas Winkler, Adam Erdelyi, and Bernhard Rinner, "TrustEYE M4: Protecting the Sensor--not the Camera", in Proceedings of the International Conference on Advanced Video and Signal Based Surveillance, 2014.
  27. ↑ S. D. Roy, Xin Li, Y. Shoshan, A. Fish, and O. Yadid-Pecht, "Hardware Implementation of a Digital Watermarking System for Video Authentication", IEEE Transactions on Circuits and Systems for Video Technology, Vol. 23, Issue 2, 2013, pp. 289-301.
  28. ↑ C. -T. Yen, T. -C. Wu, M. -H. Guo, C. -K. Yang, and H. -C. Chao, "Digital product transaction mechanism for electronic auction environment", IET Information Security, Vol. 4, Issue 4, 2010, pp. 248–257.
  29. ↑ S. P. Mohanty, N. Ranganathan, and R. K. Namballa, "VLSI Implementation of Invisible Digital Watermarking Algorithms Towards the Development of a Secure JPEG Encoder", in Proceedings of the IEEE Workshop on Signal Processing System, pp. 183-188, 2003.
  30. ↑ S. P. Mohanty, N. Ranganathan, and K. Balakrishnan, "Design of a Low Power Image Watermarking Encoder using Dual Voltage and Frequency", in Proceedings of the 18th IEEE International Conference on VLSI Design, pp. 153-158, 2005.
  31. 1 2 3 UNT Professor Receives Editorial Appointments, Recognition, http://engineering.unt.edu/unt-professor-receives-editorial-appointments-recognition
  32. ↑ IEEE Consumer Electronics Magazine Editorial Board, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7450780
  33. ↑ VLSI Circuits and Systems Letter (VCAL) -- Editorial Board, https://www.computer.org/web/tcvlsi/editorial-board
  34. ↑ Editorial Board, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), http://ieee-ceda.org/publications/tcad/editorial-board
  35. ↑ Editorial Board, ACM Journal on Emerging Technologies in Computing Systems (JETC), http://jetc.acm.org/editorial_board.cfm
  36. ↑ IEEE Consumer Electronics Magazine (MCE) -- IEEE Consumer Electronics Magazine Editorial Board Member Roster, http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7308143
  37. ↑ IET Circuits, Devices and Systems (CDS) -- Editorial board, http://digital-library.theiet.org/journals/iet-cds/editorial-board
  38. ↑ Integration, the VLSI Journal -- Editorial Board, http://www.journals.elsevier.com/integration-the-vlsi-journal/editorial-board/
  39. ↑ ASP Journal of Low Power Electronics (JOLPE) -- Editorial Board, http://www.aspbs.com/jolpe/editorial_jolpe.htm
  40. ↑ Special Issue on Circuit and System Design Automation for Internet of Things, https://mc.manuscriptcentral.com/societyimages/tcad/CFP_Special-Circuit%20and%20System%20Design%20Automation%20for%20Internet%20of%20Things.pdf
  41. ↑ IEEE Transactions on Nanotechnology (TNANO) -- Nanoelectronic Devices and Circuits for Next Generation Sensing and Information Processing, http://sites.ieee.org/tnano/2015/12/special-issue-ion-processing/
  42. ↑ ACM Journal on Emerging Technologies in Computing Systems (JETC) -- Nanoelectronic Circuit and System Design Methods for Mobile Computing Era, http://jetc.acm.org/pdf/ACM-JETC_SI_NanoMobi_CFP.pdf
  43. ↑ Elsevier The VLSI Integration Journal (Integration) -- Hardware Assisted Techniques for IoT and Bigdata Applications, http://www.journals.elsevier.com/integration-the-vlsi-journal/call-for-papers/special-issue-on-hardware-assisted-techniques-for-iot/
  44. ↑ IEEE Access -- Security and Reliability Aware System Design for Mobile Computing Systems, http://www.ieee.org/publications_standards/publications/ieee_access/security_reliability.pdf
  45. ↑ IEEE Transactions on Emerging Topics in Computing (TETC) -- Circuit and System Design Methodologies for Emerging Technologies, Vol. 3, No. 4, October–December 2015, http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6245516
  46. ↑ Springer Circuits, Systems, and Signal Processing Journal (CSSP), Volume 32, Issue 6, December 2013, http://link.springer.com/journal/34/32/6/page/1
  47. ↑ IET Circuits, Devices, & Systems Journal (CDS), Volume 7, issue 5, September 2013, http://digital-library.theiet.org/content/journals/iet-cds/7/5#headline1
  48. ↑ ACM Journal on Emerging Technologies in Computing Systems (JETC), Volume 8, Issue 3, August 2012, http://portalparts.acm.org/2290000/2287696/fm/frontmatter.pdf?ip=173.74.56.32&CFID=735311818&CFTOKEN=90085137
  49. ↑ ASP Journal of Low Power Electronics (JOLPE), Volume 8, Issue 3, June 2012, http://www.aspbs.com/jolpe/contents_jolpe2012.htm#v8n3
  50. ↑ Elsevier International Journal on Computers and Electrical Engineering, Volume 35, Issue 2, March 2009, http://www.sciencedirect.com/science/journal/00457906/35/2
  51. ↑ IEEE Computer Society Annual Symposium on VLSI (ISVLSI), http://www.isvlsi.org
  52. ↑ IEEE International Symposium on Nanoelectronic and Information Systems (IEEE-iNIS), http://www.ieee-inis.org/
  53. ↑ International Conference on Information Technology (ICIT), http://www.oits-icit.org
  54. ↑ Orissa Information Technology Society, http://www.oits.org
  55. ↑ International Symposium on Nanoelectronic and Information Systems (IEEE iNIS 2015), 21–23 December 2015, Indore, India, http://www.globaleventslist.elsevier.com/events/2015/12/international-symposium-on-nanoelectronic-and-information-systems-inis/
  56. ↑ Computer Science and Engineering Researcher Chairs International Symposium, August 2015, http://engineering.unt.edu/computer-science-and-engineering-researcher-chairs-international-symposium
  57. ↑ IEEE’s first intl symposium on iNIS to be held in City, Aug 17, 2015, http://www.freepressjournal.in/ieees-first-intl-symposium-on-inis-to-be-held-in-city/
  58. ↑ A student research symposium was organised by ISTE-Silicon Student chapter - See more at: http://www.orissadiary.com/CurrentNews.asp?id=56591#sthash.iP2IFtmy.dpuf
  59. ↑ The International Conference on Information Technology (ICIT), http://www.oits-icit.org
  60. ↑ Orissa Information Technology Society (OITS), http://www.oits.org/
  61. ↑ The 22nd International Conference on VLSI Design -- Unified Challenges in Nano-CMOS High-Level Synthesis, 2009, http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=4749726&newsearch=true&queryText=Unified%20Challenges%20in%20Nano-CMOS%20High-Level%20Synthesis
  62. ↑ Technical & Conferences Activities Board -- Technical Committees -- Technical Committee on VLSI, http://www.computer.org/web/tandc/tcvlsi
  63. ↑ Dr. Saraju Mohanty Serves as the Chair of the Technical Committee on Very Large Scale Integration (TCVLSI), http://www.cse.unt.edu/site/node/678
  64. ↑ 2016 PROSE Award Winners, https://proseawards.com/winners/2016-award-winners/#body
  65. ↑ Saraju Mohanty wins McGraw-Hill textbook award, https://facultysuccess.unt.edu/faculty-awards/saraju-mohanty-wins-mcgraw-hill-textbook-award
  66. ↑ ISVLSI 2015, http://www.eng.ucy.ac.cy/theocharides/isvlsi15/
  67. ↑ USF Notable Alumnus, Bulls to Brag About, USF Alumni Association Website.
  68. ↑ Indian Institute of Science Notable Alumnus, Indian Institute of Science.
  69. ↑ College of Engineering and Technology, Bhubaneswar Notable Alumnus, College of Engineering and Technology, Bhubaneswar
  70. ↑ CET Rising, Interviewed: Mr. Saraju Mohanty, Interview Taken by: Trishala Mishra, Saturday, 29 August 2015, http://rising.cetb.in/2015/08/interviewed-mr-saraju-mohanty.html
  71. ↑ Engineering Professors Awarded Multiple Patents to Innovate Integrated Circuit Design, UNT Faculty Success Newsletter, October 2015, https://facultysuccess.unt.edu/unt-faculty-newsletter-october-2015-edition.
  72. ↑ Researchers Receive Patent for a Method for Designing Complex, Mixed-signal Circuits, October 2015, http://engineering.unt.edu/researchers-receive-patent-method-designing-complex-mixed-signal-circuits
  73. ↑ Researchers Awarded Patent for Method to Innovate Mixed-signal Integrated Circuit Design, May 2015, http://engineering.unt.edu/researchers-awarded-patent-method-innovate-mixed-signal-integrated-circuit-design
  74. ↑ Methodology for Nanoscale Technology based Mixed-Signal System Design, US Patent Number: 9,053,276, Issued on: 9th June 2015 http://assignment.uspto.gov/#/assignment?id=30967-123&q=patAssignorName%3A(MOHANTY%2C%20AND%20SARAJU%20AND%20P.)
  75. ↑ Intelligent Metamodel Integrated Verilog-AMS for Fast and Accurate Analog Block Design Exploration, US Patent Number: 9,026,964, Issued on: 5th May 2015 http://assignment.uspto.gov/#/assignment?id=32972-875&q=patAssignorName%3A(MOHANTY%2C%20AND%20SARAJU%20AND%20P.)
  76. ↑ Apparatus and Method for Transmitting Secure and/or Copyrighted Digital Video Broadcasting Data Over Internet Protocol Network, US Patent Number: 8,423,778, Issued on: 16th Apr 2013 http://assignment.uspto.gov/#/assignment?id=22252-43&q=patAssignorName%3A(MOHANTY%2C%20AND%20SARAJU%20AND%20P.)
  77. ↑ Methods and Devices for Enrollment and Verification of Biometric Information in Identification Documents, US Patent Number: 8,058,972, Issued on: 15th Nov 2011 http://assignment.uspto.gov/#/assignment?id=21372-691&q=patAssignorName%3A(MOHANTY%2C%20AND%20SARAJU%20AND%20P.)
  78. ↑ http://www.mhprofessional.com/product.php?isbn=0071825711
  79. ↑ Saraju Mohanty wins McGraw-Hill textbook award, http://www.cse.unt.edu/site/node/677
  80. ↑ http://www.theiet.org/resources/books/circuits/nano-cmos-post-cmos-vol1.cfm
  81. ↑ http://www.theiet.org/resources/books/circuits/Ncmosvol2.cfm
  82. ↑ http://www.springer.com/engineering/circuits+%26+systems/book/978-1-4614-08178
  83. ↑ http://www.springer.com/engineering/circuits+%26+systems/book/978-0-387-76473-3
  84. ↑ Prof. Nagarajan "Ranga" Ranganathan, Ph.D. Distinguished University Professor, http://cans.cse.usf.edu/faculty/ranga/
  85. ↑ K. R. Ramakrishnan, Professor, Department of Electrical Engineering, Indian Institute of Science, http://www.ee.iisc.ernet.in/new/people/faculty/krr/index.html
  86. ↑ Mohan S. Kankanhalli, Vice Provost (Graduate Education), National University of Singapore, Professor, Department of Computer Science, School of Computing, http://www.comp.nus.edu.sg/~mohan/
  87. ↑ Prof. N. Balakrishnan, http://www.serc.iisc.ernet.in/~balki/
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