DDR4 SDRAM

This article is about DDR4 SDRAM. For graphics DDR4, see GDDR4. For the video game, see Dance Dance Revolution 4thMix.
DDR4 SDRAM

Two 8 GiB DDR4-2133 ECC 1.2 V RDIMMs[lower-alpha 1]
Type Synchronous dynamic random-access memory (SDRAM)
Release date September 2014[1]
Predecessor DDR3 SDRAM
Website www.jedec.org/standards-documents/results/jesd79-4%20ddr4

In computing, DDR4 SDRAM, an abbreviation for double data rate fourth-generation synchronous dynamic random-access memory, is a type of synchronous dynamic random-access memory (SDRAM) with a high bandwidth ("double data rate") interface. Released to the market in 2014,[2][3][4] it is one of the latest variants of dynamic random-access memory (DRAM), some of which have been in use since the early 1970s,[5] and a higher-speed successor to the DDR2 and DDR3 technologies. It is not compatible with any earlier type of random access memory (RAM) due to different signaling voltages, physical interface and other factors.

DDR4 SDRAM was released to the public market in Q2 2014, focusing on ECC memory,[6] while the non-ECC DDR4 modules became available in Q3 2014, accompanying the launch of Haswell-E processors that require DDR4 memory.[7]

Features

The primary advantages of DDR4 over its predecessor, DDR3, include higher module density and lower voltage requirements, coupled with higher data rate transfer speeds. The DDR4 standard theoretically allows for DIMMs of up to 512 GiB in capacity, compared to the DDR3's theoretical maximum of 128 GiB per DIMM.[8]

DDR4 operates at a voltage of 1.2 V with a frequency between 800 and 1600 MHz, compared to frequencies between 400 and 1067 MHz[9][lower-alpha 2] and voltage requirements of 1.5 or 1.65 V of DDR3. Although a low-voltage standard has yet to be finalized (as of August 2014), it is anticipated that low-voltage DDR4 will run at a voltage of 1.05 V, compared to DDR3's low-voltage standard (DDR3L) which requires 1.35 V to operate.[11]

History

The first DDR4 memory module prototype was manufactured by Samsung and announced in January 2011.[lower-alpha 3]

Standards body JEDEC began working on a successor to DDR3 around 2005,[13] about 2 years before the launch of DDR3 in 2007.[14][15] The high-level architecture of DDR4 was planned for completion in 2008.[16]

Some advance information was published in 2007,[17] and a guest speaker from Qimonda provided further public details in a presentation at the August 2008 San Francisco Intel Developer Forum (IDF).[17][18][19][20] DDR4 was described as involving a 30 nm process at 1.2 volts, with bus frequencies of 2133 MT/s "regular" speed and 3200 MT/s "enthusiast" speed, and reaching market in 2012, before transitioning to 1 volt in 2013.[18][20]

Subsequently, further details were revealed at MemCon 2010, Tokyo (a computer memory industry event), at which a presentation by a JEDEC director titled "Time to rethink DDR4"[21] with a slide titled "New roadmap: More realistic roadmap is 2015" led some websites to report that the introduction of DDR4 was probably[22] or definitely[23][24] delayed until 2015. However, DDR4 test samples were announced in line with the original schedule in early 2011 at which time manufacturers began to advise that large scale commercial production and release to market was scheduled for 2012.[2]

DDR4 was expected to represent 5% of the DRAM market in 2013,[2] and to reach mass market adoption and 50% market penetration around 2015;[2] as of 2013, however, adoption of DDR4 has been delayed and it is no longer expected to reach a majority of the market until 2016 or later.[25] The transition from DDR3 to DDR4 is thus taking longer than the approximately five years taken for DDR3 to achieve mass market transition over DDR2.[26] In part, this is because changes required to other components would affect all other parts of computer systems, which would need to be updated to work with DDR4.[27]

In February 2009, Samsung validated 40 nm DRAM chips, considered a "significant step" towards DDR4 development[28] since in 2009, DRAM chips were only beginning to migrate to a 50 nm process.[29] In January 2011, Samsung announced the completion and release for testing of a 2 GiB DDR4 DRAM module based on a process between 30 and 39 nm.[30] It has a maximum data transfer rate of 2133 MT/s at 1.2 V, uses pseudo open drain technology (adapted from graphics DDR memory[31]) and draws 40% less power than an equivalent DDR3 module.[30][32][33]

Three months later in April 2011, Hynix announced the production of 2 GiB DDR4 modules at 2400 MT/s, also running at 1.2 V on a process between 30 and 39 nm (exact process unspecified),[2] adding that it anticipated commencing high volume production in the second half of 2012.[2] Semiconductor processes for DDR4 are expected to transition to sub-30 nm at some point between late 2012 and 2014.[26][34]

In May 2012, Micron announced[3] it is aiming at starting production in late 2012 of 30 nm modules.

In July 2012, Samsung Electronics Co., Ltd., announced that it has begun sampling the industry's first 16 GiB registered dual inline memory modules (RDIMMs) using DDR4 SDRAM for enterprise server systems.[35][36]

In September 2012, JEDEC released the final specification of DDR4.[1]

In April 2014, Hynix announced that it has developed the world's first highest-density 128 GiB module based on 8 Gib DDR4 using 20 nm technology. The module works at 2133 MHz, with a 64-bit I/O, and processes up to 17 GB of data per second. Hynix expects DDR4 SDRAM to be commercialized by 2015, and turned into a standard by 2016.[37]

Market perception and adoption

In April 2013, a news writer at International Data Group (IDG)—​​an American technology research business originally part of IDC—​​produced an analysis of their perceptions related to DDR4 SDRAM.[38] The conclusions were that the increasing popularity of mobile computing and other devices using slower but low-powered memory, the slowing of growth in the traditional desktop computing sector, and the consolidation of the memory manufacturing marketplace, meant that margins on RAM were tight.

As a result, the desired premium pricing for the new technology was harder to achieve, and capacity had shifted to other sectors. SDRAM manufacturers and chipset creators were, to an extent, "stuck between a rock and a hard place" where "nobody wants to pay a premium for DDR4 products, and manufacturers don't want to make the memory if they are not going to get a premium", according to Mike Howard from iSuppli.[38] A switch in market sentiment toward desktop computing and release of processors having DDR4 support by Intel and AMD could therefore potentially lead to "aggressive" growth.[38]

Intel's 2014 Haswell roadmap revealed the company's first use of DDR4 SDRAM in Haswell-EP processors.[39]

Operation

DDR4 chips use a 1.2 V supply[40]:16[41][42] with a 2.5 V auxiliary supply for wordline boost called VPP,[40]:16 as compared with the standard 1.5 V of DDR3 chips, with lower voltage variants at 1.05 V appearing in 2013. DDR4 is expected to be introduced at transfer rates of 2133 MT/s,[40]:18 estimated to rise to a potential 4266 MT/s[27] by 2013. The minimum transfer rate of 2133 MT/s was said to be due to progress made in DDR3 speeds which, being likely to reach 2133 MT/s, left little commercial benefit to specifying DDR4 below this speed.[26][27] Techgage interpreted Samsung's January 2011 engineering sample as having CAS latency of 13 clock cycles, described as being comparable to the move from DDR2 to DDR3.[31]

Internal banks are increased to 16 (4 bank select bits), with up to 8 ranks per DIMM.[40]:16

Protocol changes include:[40]:20

Increased memory density is anticipated, possibly using TSV ("through-silicon via") or other 3D stacking processes.[26][27][43][44] The DDR4 specification will include standardized 3D stacking "from the start" according to JEDEC,[44] with provision for up to 8 stacked dies.[40]:12 X-bit Labs predicted that "as a result DDR4 memory chips with very high density will become relatively inexpensive".[27] Prefetch remains at 8n[40]:16 with bank groups, including the use of two or four selectable bank groups.[45]

Switched memory banks are also an anticipated option for servers.[26][43]

In 2008 concerns were raised in the book Wafer Level 3-D ICs Process Technology that non-scaling analog elements such as charge pumps and voltage regulators, and additional circuitry "have allowed significant increases in bandwidth but they consume much more die area". Examples include CRC error-detection, on-die termination, burst hardware, programmable pipelines, low impedance, and increasing need for sense amps (attributed to a decline in bits per bitline due to low voltage). The authors noted that, as a result, the amount of die used for the memory array itself has declined over time from 70–78% with SDRAM and DDR1, to 47% for DDR2, to 38% for DDR3 and potentially to less than 30% for DDR4.[46]

The specification defined standards for ×4, ×8 and ×16 memory devices with capacities of 2, 4, 8 and 16 Gib.[47]

Command encoding

Although it still operates in fundamentally the same way, DDR4 makes one major change to the command formats used by previous SDRAM generations. A new command signal /ACT is low to indicate the activate (open row) command.

The activate command requires more address bits than any other (18 row address bits in an 8 Gb part), so the standard /RAS, /CAS and /WE signals are shared with high-order address bits that are not used when /ACT is high. The combination of /RAS=L, /CAS=H and /WE=H that previously encoded an activate command is unused.

As in previous SDRAM encodings, A10 is used to select command variants: auto-precharge on read and write commands, and one bank vs. all banks for the precharge command. It also selects two variants of the ZQ calibration command.

In addition, A12 is used to request burst chop: truncation of an 8-transfer burst after four transfers. Although the bank is still busy and unavailable for other commands until eight transfer times have elapsed, a different bank can be accessed.

Also, the number of bank addresses has been increased greatly. There are four bank select bits to select up to 16 banks within each DRAM: two bank address bits (BA0, BA1), and two bank group bits (BG0, BG1). There are additional timing restrictions when accessing banks within the same bank group; it is faster to access a bank in a different bank group.

In addition, there are three chip select signals (C0, C1, C2), allowing up to eight stacked chips to be placed inside a single DRAM package. These effectively act as three more bank select bits, bringing the total to 7 (128 possible banks).

DDR4 command encoding[48]
/CS BGn, BAn /ACT A17 A16
/RAS 		A15
/CAS 		A14
/WE 		A13 A12 A11 A10 A9–0 Command
H — x —[lower-alpha 4] Deselect (No operation)
L bank L Row address Active (activate): open a row
L x H x H H H — x — No operation
L x H x H H L x long x ZQ Calibration
L bank H x H L H x BC x AP Column Read (BC=burst chop)
L bank H x H L L x BC x AP Column Write (AP=auto-precharge)
L x H x L H H — x — (Unassigned, reserved)
L x H x L H L x H x Precharge all banks
L bank H x L H L x L x Precharge one bank
L x H x L L H — x — Refresh
L register H 0 L L L 0 data Mode register set (MR0–MR6)

Standard transfer rates are 1600, 1866, 2133 and 2400 MT/s.[48] (12/15, 14/15, 16/15 and 18/15 GHz clock speeds, double data rate.) 2666 and 3200 MT/s (20/15 and 24/15 GHz clock speeds) are provided for, but the specifications are not yet complete.

Design considerations

The DDR4 team at Micron Technology identified some key points for IC and PCB design:[49]

IC design:[49]

Circuit board design:[49]

Module packaging

DDR4 memory is supplied in 288-pin dual in-line memory modules (DIMMs), similar in size to 240-pin DDR3 DIMMs. The pins are spaced more closely (0.85 mm instead of 1.0) to fit the increased number within the same 5¼ inch (133.35 mm) standard DIMM length, but the height is increased slightly (31.25 mm/1.23 in instead of 30.35 mm/1.2 in) to make signal routing easier, and the thickness is also increased (to 1.2 mm from 1.0) to accommodate more signal layers.[50] DDR4 DIMM modules have a slightly curved edge connector so not all of the pins are engaged at the same time during module insertion, lowering the insertion force.[12]

DDR4 SO-DIMMs have 260 pins instead of the 204 pins of DDR3 SO-DIMMs, spaced at 0.5 rather than 0.6 mm, and are 2.0 mm wider (69.6 versus 67.6 mm), but remain the same 30 mm in height.[51]

For its Skylake microarchitecture, Intel designed a SO-DIMM package named UniDIMM, which can be populated with either DDR3 or DDR4 chips. At the same time, the integrated memory controller (IMC) of Skylake CPUs is announced to be capable of working with either type of memory. The purpose of UniDIMMs is to help in the market transition from DDR3 to DDR4, where pricing and availability may make it undesirable to switch the RAM type. UniDIMMs have the same dimensions and number of pins as regular DDR4 SO-DIMMs, but the edge connector's notch is placed differently to avoid accidental use in incompatible DDR4 SO-DIMM sockets.[52]

Modules

JEDEC standard DDR4 module[53][54]

Standard name

 

 Memory clock

(MHz)

 I/O bus clock

(MHz)

 Data rate

(MT/s)

 Module name

 

 Peak transfer rate

(MB/s)

 Timings

(CL-tRCD-tRP)

 CAS latency

(ns)

DDR4-1600J*
DDR4-1600K
DDR4-1600L 		200 800 1600 PC4-1600 12800 10-10-10
11-11-11
12-12-12 		12.5
13.75
15
DDR4-1866L*
DDR4-1866M
DDR4-1866N 		233.33 933.33 1866.67 PC4-1866 14933.33 12-12-12
13-13-13
14-14-14 		12.857
13.929
15
DDR4-2133N*
DDR4-2133P
DDR4-2133R 		266.67 1066.67 2133.33 PC4-2133 17066.67 14-14-14
15-15-15
16-16-16 		13.125
14.063
15
DDR4-2400P*
DDR4-2400R
DDR4-2400U 		300 1200 2400 PC4-2400 19200 15-15-15
16-16-16
18-18-18 		12.5
13.33
15

* optional

CL (CAS Latency) - Clock cycles between sending a column address to the memory and the beginning of the data in response

tRCD - Clock cycles between row activate and reads/writes

tRP - Clock cycles between row precharge and activate

DDR4-xxxx and PC4-xxxx both denote per-bit data transfer rate, the former for DDR chips and the latter for modules (assembled DIMMs). It can be seen that the DDR4 module names are done differently than prior generations (e.g. DDR3), by using the per-bit data rate rather than the overall byte transfer rate (e.g. PC4-1866 vs. PC3-14900, both representing the same peak transfer rate). Module peak transfer rate is calculated by taking transfers per second and multiplying by eight. This is because DDR4 memory modules transfer data on a bus that is 64 data bits wide, and since a byte comprises 8 bits, this equates to 8 bytes of data per transfer.

Successor

As of 2014, no direct successor technology is planned, which would presumably be named "DDR5 SDRAM". Some sources speculate that the next memory standard would more likely use a serial interface, instead of a parallel interface currently used by the DDR4's 288/260-pin unregistered variants, and mention the most prominent example of Micron Technology's Hybrid Memory Cube (HMC) stacked memory. The historical progression of other computer buses toward replacing parallel buses with serial buses are exampled by the evolution of Serial ATA replacing Parallel ATA, PCI Express replacing PCI, and serial ports replacing parallel ports. In general, serial buses are easier to scale up and have fewer wires/traces, making circuit boards using them easier to design.[55][56][57]

In 2011, JEDEC also published the Wide I/O 2 standard; like the Hybrid Memory Cube, it stacks multiple memory dies, but does that directly on top of the CPU and in the same package. This memory layout provides higher bandwidth and better power performance than DDR4 SDRAM, and allows a wide interface with short signal lengths. It primarily aims to replace various mobile DDRX SDRAM standards used in high-performance embedded and mobile devices, such as smartphones.[58][59] Hynix proposed similar High Bandwidth Memory (HBM), which was published as JEDEC JESD235. Both Wide I/O 2 and HBM use a very wide parallel memory interface, up to 512 bits wide for Wide I/O 2 (compared to 64 bits for DDR4), running at a lower frequency than DDR4.[60]

Wide I/O 2 is targeted at high-performance compact devices such as smartphones, where it will be integrated into the processor or system on a chip (SoC) packages. HBM is targeted at graphics memory and general computing, while HMC targets high-end servers and enterprise applications.[60]

GDDR5 SGRAM is a graphics type of DDR3 synchronous graphics RAM, which was introduced before DDR4, and is not a successor to DDR4.

See also

Notes

  1. ↑ This is actually a kit of four DDR4 RDIMMs, and the third one is partially visible in the picture.
  2. ↑ Some factory-overclocked DDR3 memory modules operate at higher frequencies, up to 1600 MHz.[10]
  3. ↑ As a prototype, this DDR4 memory module has a flat edge connector at the bottom, while production DDR4 DIMM modules have a slightly curved edge connector so not all of the pins are engaged at a time during module insertion, lowering the insertion force.[12]
  4. ↑ Bits marked with "x" are "do not care", but must be at a valid voltage level, either zero or one.

References

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  3. 1 2 Micron teases working DDR4 RAM, Engadget, 2012-05-08, retrieved 2012-05-08
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  5. ↑ The DRAM Story (PDF), IEEE, 2008, p. 10, retrieved 2012-01-23
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  17. 1 2 "DDR4 – the successor to DDR3 memory". The "H" (online ed.). 2008-08-21. Archived from the original on 26 May 2011. Retrieved 2011-04-28. The JEDEC standardisation committee cited similar figures around one year ago
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  30. 1 2 "Samsung Develops Industry's First DDR4 DRAM, Using 30nm Class Technology". Samsung. 2011-04-11. Retrieved 26 April 2011.
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  36. ↑ "Samsung Samples Industry’s First 16-Gigabyte Server Modules Based on DDR4 Memory technology" (press release). Samsung.
  37. ↑ "SK Hynix Developed the World’s First Highest Density 128GB DDR4 Module" (press release). Skhynix.
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  39. ↑ "Haswell-E - Intel's First 8 Core Desktop Processor Exposed". TechPowerUp.
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  52. ↑ "How Intel Plans to Transition Between DDR3 and DDR4 for the Mainstream". Tech Power Up.
  53. ↑ JESD79-4A – JEDEC Standard DDR4 SDRAM November 2013 (PDF), JEDEC
  54. ↑ DDR4 SDRAM UDIMM Design Specification (PDF), JEDEC
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