Transistor count
The transistor count is the number of transistors on an integrated circuit chip. Transistor count is the most common measure of semiconductor integrated circuit complexity. As of 2015, the highest transistor count in a commercially available CPU (in one chip) is over 5.5 billion transistors, in Intel's 18-core Xeon Haswell-EP.
According to Moore's law the transistor count of the integrated circuits doubles approximately every two years. On most modern microprocessors, the majority of transistors are contained in caches. In fact, IBM's Storage Controller at 7.1 billion transistors with 480 MB L4 cache in 2015, is bigger than any microprocessor before, on both counts; it is however not a CPU until combined with one (or more) of its companion IBM z13 microprocessor chip. That chip holds the rest of the cache, 64 MB L3 (and the other smaller levels) and processor logic, and while having the same dimensions has only 3.9 billion transistors (near record breaking for a microprocessor on its own). To date, combined, this mainframe is the biggest general purpose processor when only one Storage Controller is used, let alone when two are used.
On August 7, 2014, IBM announced their neuromorphic TrueNorth chip; their second generation chip backed by the SyNAPSE program, which, with 5.4 billion transistors (in 4096 cores), has more transistors than any chip IBM has ever made[1] (until their Storage Controller, mentioned above) and is the "second largest (CMOS) chip in the world"[2][3][4] (and therefore the largest "neuromorphic" one, as a GPU chip is bigger, but sixteen can be connected together).
Xilinx currently holds the "world-record" for a FPGA containing more than 20 billion transistors.
Microprocessors
A microprocessor incorporates the functions of a computer's central processing unit on a single integrated circuit. It is a multipurpose, programmable device that accepts digital data as input, processes it according to instructions stored in its memory, and provides results as output.
Processor | Transistor count | Date of introduction | Designer | Process | Area |
---|---|---|---|---|---|
TMS 1000 | 8,000 | 1971 | Texas Instruments | 8,000 nm | |
Intel 4004 | 2,300 | 1971 | Intel | 10,000 nm | 12 mm² |
Intel 8008 | 3,500 | 1972 | Intel | 10,000 nm | 14 mm² |
MOS Technology 6502 | 3,510[5] | 1975 | MOS Technology | 8,000 nm | 21 mm² |
Motorola 6800 | 4,100 | 1974 | Motorola | 6,000 nm | 16 mm² |
Intel 8080 | 4,500 | 1974 | Intel | 6,000 nm | 20 mm² |
RCA 1802 | 5,000 | 1974 | RCA | 5,000 nm | 27 mm² |
Intel 8085 | 6,500 | 1976 | Intel | 3,000 nm | 20 mm² |
Zilog Z80 | 8,500 | 1976 | Zilog | 4,000 nm | 18 mm² |
Motorola 6809 | 9,000 | 1978 | Motorola | 5,000 nm | 21 mm² |
Intel 8086 | 29,000 | 1978 | Intel | 3,000 nm | 33 mm² |
Intel 8088 | 29,000 | 1979 | Intel | 3,000 nm | 33 mm² |
WDC 65C02 | 11,500[6] | 1981 | WDC | 3,000 nm | 6 mm² |
Intel 80186 | 55,000 | 1982 | Intel | 3,000 nm | 60 mm² |
Motorola 68000 | 68,000 | 1979 | Motorola | 3,500 nm | 44 mm² |
Intel 80286 | 134,000 | 1982 | Intel | 1,500 nm | 49 mm² |
WDC 65C816 | 22,000[7] | 1983 | WDC | 9 mm² | |
Motorola 68020 | 190,000[8] | 1984 | Motorola | 2,000 nm | 85 mm² |
Intel 80386 | 275,000 | 1985 | Intel | 1,500 nm | 104 mm² |
ARM 1 | 25,000[8] | 1985 | Acorn | 3,000 nm | 50 mm² |
Novix NC4016 | 16,000[9] | 1985[10] | Harris Corporation | 3,000 nm[11] | |
ARM 2 | 30,000[8] | 1986 | Acorn | 2,000 nm | 30 mm² |
TI Explorer's 32-bit Lisp machine chip | 553,000[12] | 1987 | Texas Instruments | ||
DEC WRL MultiTitan | 180,000[13] | 1988 | DEC WRL | 1,500 nm | 61 mm² |
Intel i960 | 250,000[14] | 1988 | Intel | 600 nm | |
Intel 80486 | 1,180,235 | 1989 | Intel | 1000 nm | 173 mm² |
ARM 3 | 300,000 | 1989 | Acorn | ||
R4000 | 1,350,000 | 1991 | MIPS | 1,000 nm | 213 mm² |
ARM 6 | 35,000 | 1991 | ARM | ||
Pentium | 3,100,000 | 1993 | Intel | 800 nm | 294 mm² |
ARM700 | 578,977[15] | 1994 | ARM | 68.51 mm² | |
SA-110 | 2,500,000[8] | 1995 | Acorn/DEC/Apple | 350 nm | 50 mm² |
ARM 9TDMI | 111,000[8] | 1999 | Acorn | 350 nm | 4.8 mm² |
Pentium Pro | 5,500,000[16] | 1995 | Intel | 500 nm | 307 mm² |
AMD K5 | 4,300,000 | 1996 | AMD | 500 nm | 251 mm² |
Pentium II Klamath | 7,500,000 | 1997 | Intel | 350 nm | 195 mm² |
Pentium II Deschutes | 7,500,000 | 1998 | Intel | 250 nm | 113 mm² |
AMD K6 | 8,800,000 | 1997 | AMD | 350 nm | 162 mm² |
Pentium III Katmai | 9,500,000 | 1999 | Intel | 250 nm | 128 mm² |
Pentium III Coppermine | 21,000,000 | 2000 | Intel | 180 nm | 80 mm² |
Pentium II Mobile Dixon | 27,400,000 | 1999 | Intel | 180 nm | 180 mm² |
Pentium III Tualatin | 45,000,000 | 2001 | Intel | 130 nm | 81 mm² |
AMD K6-III | 21,300,000 | 1999 | AMD | 250 nm | 118 mm² |
AMD K7 | 22,000,000 | 1999 | AMD | 250 nm | 184 mm² |
Pentium 4 Willamette | 42,000,000 | 2000 | Intel | 180 nm | 217 mm² |
Pentium 4 Northwood | 55,000,000 | 2002 | Intel | 130 nm | 145 mm² |
Pentium 4 Prescott | 112,000,000 | 2004 | Intel | 90 nm | 110 mm² |
Pentium 4 Prescott-2M | 169,000,000 | 2005 | Intel | 90 nm | 143 mm² |
Pentium 4 Cedar Mill | 184,000,000 | 2006 | Intel | 65 nm | 90 mm² |
Pentium D Smithfield | 228,000,000 | 2005 | Intel | 90 nm | 206 mm² |
Pentium D Presler | 362,000,000 | 2006 | Intel | 65 nm | 162 mm² |
Atom | 47,000,000 | 2008 | Intel | 45 nm | 24 mm² |
Barton | 54,300,000 | 2003 | AMD | 130 nm | 101 mm² |
AMD K8 | 105,900,000 | 2003 | AMD | 130 nm | 193 mm² |
Itanium 2 McKinley | 220,000,000 | 2002 | Intel | 180 nm | 421 mm² |
Cell | 241,000,000 | 2006 | Sony/IBM/Toshiba | 90 nm | 221 mm² |
Core 2 Duo Conroe | 291,000,000 | 2006 | Intel | 65 nm | 143 mm² |
Core 2 Duo Allendale | 169,000,000 | 2007 | Intel | 65 nm | 111 mm² |
Itanium 2 Madison 6M | 410,000,000 | 2003 | Intel | 130 nm | 374 mm² |
AMD K10 quad-core 2M L3 | 463,000,000[17] | 2007 | AMD | 65 nm | 283 mm² |
ARM Cortex-A9 | 26,000,000[18] | 2007 | ARM | 45 nm | 31 mm² |
Core 2 Duo Wolfdale 3M | 230,000,000 | 2008 | Intel | 45 nm | 83 mm² |
Itanium 2 with 9 MB cache | 592,000,000 | 2004 | Intel | 130 nm | 432 mm² |
Core 2 Duo Wolfdale | 411,000,000 | 2007 | Intel | 45 nm | 107 mm² |
Core i7 (Quad) | 731,000,000 | 2008 | Intel | 45 nm | 263 mm² |
AMD K10 quad-core 6M L3 | 758,000,000[17] | 2008 | AMD | 45 nm | 258 mm² |
POWER6 | 789,000,000 | 2007 | IBM | 65 nm | 341 mm² |
Six-core Opteron 2400 | 904,000,000 | 2009 | AMD | 45 nm | 346 mm² |
16-core SPARC T3 | 1,000,000,000[19] | 2010 | Sun/Oracle | 40 nm | 377 mm² |
Apple A7 (dual-core ARM64 "mobile SoC") | 1,000,000,000 | 2013 | Apple | 28 nm | 102 mm² |
Quad-core + GPU Core i7 | 1,160,000,000 | 2011 | Intel | 32 nm | 216 mm² |
Six-core Core i7 (Gulftown) | 1,170,000,000 | 2010 | Intel | 32 nm | 240 mm² |
8-core POWER7 32M L3 | 1,200,000,000 | 2010 | IBM | 45 nm | 567 mm² |
8-core AMD Bulldozer | 1,200,000,000[20] | 2012 | AMD | 32 nm | 315 mm² |
Quad-core + GPU AMD Trinity | 1,303,000,000 | 2012 | AMD | 32 nm | 246 mm² |
Quad-core z196[21] | 1,400,000,000 | 2010 | IBM | 45 nm | 512 mm² |
Quad-core + GPU Core i7 Ivy Bridge | 1,400,000,000 | 2012 | Intel | 22 nm | 160 mm² |
Quad-core + GPU Core i7 Haswell | 1,400,000,000[22] | 2014 | Intel | 22 nm | 177 mm² |
Dual-core Itanium 2 | 1,700,000,000[23] | 2006 | Intel | 90 nm | 596 mm² |
Quad-core + GPU GT2 Core i7 Skylake K | cca 1,750,000,000 | 2015 | Intel | 14 nm | 122 mm² |
Six-core Core i7 Ivy Bridge E | 1,860,000,000 | 2013 | Intel | 22 nm | 256 mm² |
Duo-core + GPU Iris Core i7 Broadwell-U | 1,900,000,000[24] | 2015 | Intel | 14 nm | 133 mm² |
Six-core Xeon 7400 | 1,900,000,000 | 2008 | Intel | 45 nm | 503 mm² |
Quad-core Itanium Tukwila | 2,000,000,000[25] | 2010 | Intel | 65 nm | 699 mm² |
Apple A8 (dual-core ARM64 "mobile SoC") | 2,000,000,000 | 2014 | Apple | 20 nm | 89 mm² |
8-core POWER7+ 80 MB L3 cache | 2,100,000,000 | 2012 | IBM | 32 nm | 567 mm² |
Six-core Core i7/8-core Xeon E5 (Sandy Bridge-E/EP) |
2,270,000,000[26] | 2011 | Intel | 32 nm | 434 mm² |
8-core Xeon Nehalem-EX | 2,300,000,000[27] | 2010 | Intel | 45 nm | 684 mm² |
8-core Core i7 Haswell-E | 2,600,000,000[28] | 2014 | Intel | 22 nm | 355 mm² |
10-core Xeon Westmere-EX | 2,600,000,000 | 2011 | Intel | 32 nm | 512 mm² |
Six-core zEC12 | 2,750,000,000 | 2012 | IBM | 32 nm | 597 mm² |
Apple A8X (tri-core ARM64 "mobile SoC") | 3,000,000,000[29] | 2014 | Apple | 20 nm | 128 mm² |
8-core Itanium Poulson | 3,100,000,000 | 2012 | Intel | 32 nm | 544 mm² |
IBM z13 | 3,990,000,000 | 2015 | IBM | 22 nm | 678 mm² |
12-core POWER8 | 4,200,000,000 | 2013 | IBM | 22 nm | 650 mm² |
15-core Xeon Ivy Bridge-EX | 4,310,000,000[30] | 2014 | Intel | 22 nm | 541 mm² |
61-core Xeon Phi | 5,000,000,000[31] | 2012 | Intel | 22 nm | 350 mm² |
Xbox One main SoC | 5,000,000,000 | 2013 | Microsoft/AMD | 28 nm | 363 mm² |
18-core Xeon Haswell-E5 | 5,560,000,000[32] | 2014 | Intel | 22 nm | 661 mm² |
IBM z13 Storage Controller | 7,100,000,000 | 2015 | IBM | 22 nm | 678 mm² |
22-core Xeon Broadwell-E5 | ~7,200,000,000[33] | 2016 | Intel | 14 nm | 456 mm² |
SPARC M7 | 10,000,000,000[34] | 2015 | Oracle | 20 nm |
Transistorized computers
The "second generation" of computers (transistor computers) featured boards filled with discrete transistors and magnetic memory cores.
Processor | Transistor count | Date of introduction | Manufacturer | Process | Area |
---|---|---|---|---|---|
"Transistor Computer" (full size) | 200 discrete point-contact transistors | 1955 | University of Manchester | ? | ? |
"Metrovick 950" | 200 discrete junction transistors | 1956 | Metropolitan-Vickers | ? | ? |
PDP-1 | 2,700 discrete transistors | 1959 | Digital Equipment Corporation | ||
PDP-8/s | ? discrete transistors (519 logic gates) | 1971 ? | Digital Equipment Corporation | ? | ? |
M18 FADAC | 1,600 discrete transistors | 1960 | Autonetics | ? | ? |
D-17B | 1,521 discrete transistors | 1962 | Autonetics | ? | ? |
Apollo Guidance Computer | 12,300 (4,100 ICs, each containing a single 3-transistor 3-input NOR gate) | 1966 | Raytheon / MIT Instrumentation Laboratory | ? | ? |
GPUs
A graphics processing unit (GPU) is a specialized electronic circuit designed to rapidly manipulate and alter memory to accelerate the building of images in a frame buffer intended for output to a display.
Processor | Transistor count | Date of introduction | Manufacturer | Process | Area |
---|---|---|---|---|---|
NV3 | 3,500,000 | 1997 | NVIDIA | 350 nm | 90 mm² |
Rage 128 | 8,000,000 | 1999 | AMD | 250 nm | 70 mm² |
NV5 | 15,000,000 | 1999 | Nvidia | 250 nm | |
NV10 | 23,000,000 | 1999 | Nvidia | 220 nm | 111 mm² |
NV11 | 20,000,000 | 2000 | Nvidia | 180 nm | 65 mm² |
NV15 | 25,000,000 | 2000 | Nvidia | 180 nm | 81 mm² |
R100 | 30,000,000 | 2000 | AMD | 180 nm | 97 mm² |
NV20 | 57,000,000 | 2001 | Nvidia | 150 nm | 128 mm² |
R200 | 60,000,000 | 2001 | AMD | 150 nm | 68 mm² |
NV25 | 63,000,000 | 2002 | Nvidia | 150 nm | 142 mm² |
R300 | 107,000,000 | 2002 | AMD | 150 nm | 218 mm² |
R360 | 117,000,000 | 2003 | AMD | 150 nm | 218 mm² |
NV38 | 135,000,000 | 2003 | Nvidia | 130 nm | 207 mm² |
R480 | 160,000,000 | 2004 | AMD | 130 nm | 297 mm² |
NV40 | 222,000,000 | 2004 | Nvidia | 130 nm | 305 mm² |
G70 | 303,000,000 | 2005 | Nvidia | 110 nm | 333 mm² |
R520 | 321,000,000 | 2005 | AMD | 90 nm | 288 mm² |
R580 | 384,000,000 | 2006 | AMD | 90 nm | 352 mm² |
G80 | 681,000,000 | 2006 | Nvidia | 90 nm | 480 mm² |
R600 | 700,000,000 | 2007 | AMD | 80 nm | 420 mm² |
G92 | 754,000,000 | 2007 | Nvidia | 65 nm | 324 mm² |
RV790 | 959,000,000[35] | 2008 | AMD | 55 nm | 282 mm² |
GT200 Tesla | 1,400,000,000[36] | 2008 | Nvidia | 65 nm | 576 mm² |
Cypress RV870 | 2,154,000,000[37] | 2009 | AMD | 40 nm | 334 mm² |
Cayman RV970 | 2,640,000,000 | 2010 | AMD | 40 nm | 389 mm² |
GF100 Fermi | 3,200,000,000[38] | Mar 2010 | Nvidia | 40 nm | 526 mm² |
GF110 Fermi | 3,000,000,000[38] | Nov 2010 | Nvidia | 40 nm | 520 mm² |
GK104 Kepler | 3,540,000,000[39] | 2012 | Nvidia | 28 nm | 294 mm² |
Tahiti | 4,312,711,873[40] | 2011 | AMD | 28 nm | 365 mm² |
GK110 Kepler | 7,080,000,000[41] | 2012[42] | Nvidia | 28 nm | 561 mm² |
Hawaii | 6,300,000,000 | 2013 | AMD | 28 nm | 438 mm² |
GM204 Maxwell | 5,200,000,000 | 2014 | Nvidia | 28 nm | 398 mm² |
GM200 Maxwell | 8,100,000,000 | 2015 | Nvidia | 28 nm | 601 mm² |
Fiji | 8,900,000,000 | 2015 | AMD | 28 nm | 596 mm² |
GP100 Pascal | 15,300,000,000[43] | 2016 | Nvidia | 16 nm | 610 mm² |
FPGA
A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing.
FPGA | Transistor count | Date of introduction | Manufacturer | Process | Area |
---|---|---|---|---|---|
Virtex | ~70,000,000 | 1997 | Xilinx | ||
Virtex-E | ~200,000,000 | 1998 | Xilinx | ||
Virtex-II | ~350,000,000 | 2000 | Xilinx | 130 nm | |
Virtex-II PRO | ~430,000,000 | 2002 | Xilinx | ||
Virtex-4 | 1,000,000,000 | 2004 | Xilinx | 90 nm | |
Virtex-5 | 1,100,000,000[44] | 2006 | Xilinx | 65 nm | |
Stratix IV | 2,500,000,000[45] | 2008 | Altera | 40 nm | |
Stratix V | 3,800,000,000[46] | 2011 | Altera | 28 nm | |
Virtex-7 | 6,800,000,000[47] | 2011 | Xilinx | 28 nm | |
Virtex-Ultrascale XCVU440 | 20,000,000,000+[48] | 2014 | Xilinx | 20 nm |
Logic functions
Transistor count for generic logic functions is based on static CMOS implementation.[49]
Function | Transistor count |
---|---|
NOT | 2 |
Buffer | 4 |
NAND 2-input | 4 |
NOR 2-input | 4 |
AND 2-input | 6 |
OR 2-input | 6 |
NAND 3-input | 6 |
NOR 3-input | 6 |
XOR 2-input | 6 |
XNOR 2-input | 8 |
MUX 2-input with TG | 6 |
MUX 4-input with TG | 18 |
NOT MUX 2-input | 8 |
MUX 4-input | 24 |
1-bit Adder full | 28 |
1-bit Adder–subtractor | 48 |
AND-OR-INVERT [50] | 6 |
Latch, D gated | 8 |
Flip-flop, edge triggered dynamic D with reset | 12 |
8-bit multiplier[51] | 3,000 |
16-bit multiplier[51] | 9,000 |
32-bit multiplier[52] | 21,000 |
small-scale integration | 2–100[53] |
medium-scale integration | 100–500[53] |
large-scale integration | 500–20,000[53] |
very-large-scale integration | 20,000–1,000,000[53] |
ultra-large scale integration | >1,000,000 |
Memory
Semiconductor memory is an electronic data storage device, often used as computer memory, implemented on integrated circuit.
We know that in order to store a single bit (which may be 1 or 0), one flip-flop is required, made of around eight transistors. Typical CMOS Static random-access memory (SRAM) consists of 6 transistors. For Dynamic random-access memory (DRAM), 1T1C, which means one transistor and one capacitor structure is common. Capacitor charged or not is used to store 1 or 0. For flash memory, the data is stored in floating gate, and the resistance of the transistor is sensed to interpret the data stored. Depending on how fine scale the resistance could be separated, one transistor could store up to 3-bits, meaning eight distinctive level of resistance possible per transistor. However, the fine the scale comes with cost of repeatability therefore reliability. Typically, low grade 2-bits MLC flash is used for flash drive, so a 16 GB flash drive contains roughly 64 billion transistors.
Chip | Capacity & type | Transistor count | Date of introduction | Manufacturer | Process | Area |
---|---|---|---|---|---|---|
? | 256-bit ROM bipolar TTL | ? | 1965 | Sylvania | ? | ? |
? | 1024-bit ROM MOS | ? | 1965 | General Microelectronics | ? | ? |
SP95 | 16-bit SRAM bipolar | ? | 1965 | IBM | ? | ? |
? | 128-bit RAM | ? | 1969 | IBM | ? | ? |
512-bit PROM bipolar TTL | ? | 1970 | Radiation Inc. | ? | ? | |
93400 | 256-bit RAM | ? | 1970 | Fairchild | ? | ? |
1103[54][55] | 1 kb DRAM | ?1,024 | 1970 | Intel | ? | ? |
1702 Erasable PROM | 2 kb EPROM | ? | 1971 | Intel | ? | ? |
? | 8 Mb DRAM | ?8,388,608 | January 6, 1984 (1986) | Hitachi | ? | ? |
?[56][57] | 64 Mb DRAM | ?67,108,864 | 1994 | NEC, Samsung | 320 nm | ? |
?[58][59] | 256 Mb DRAM | ?268,435,456 | June 12, 1995 | IBM, SIEMENS AG, Toshiba Corp. | 250 nm | 286 mm² |
?[60] | 1 Gb DRAM | ?1,073,741,824 | January 9, 1995 (2001) | Hitachi | ? | ? |
? | 64 Gb DRAM | ?68,719,476,736 | 2007(9)? | ? | ? | ? |
?[61] | 128 Gb DRAM | ?137,438,953,472 | July 5, 2012 | Samsung | 30 nm | ? |
Parallel systems
Historically, each processing element in earlier parallel systems—like all CPUs of that time—was a serial computer built out of multiple chips. As transistor counts per chip increases, each processing element could be built out of fewer chips, and then later each multi-core processor chip could contain more processing elements.[62]
Goodyear MPP: (1983?) 8 pixel processors per chip, 3,000 to 8,000 transistors per chip.[62]
Brunel University Scape (single-chip array-processing element): (1983) 256 pixel processors per chip, 120,000 to 140,000 transistors per chip.[62]
Cell Broadband Engine: (2006) 9 cores per chip, 234 million transistors per chip.[63]
References
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- ↑ Intel: 35 Years of Innovation (1968–2003) Intel, 2003
- ↑ The DRAM memory of Robert Dennard history-computer.com
- ↑ NEC to build 64-Mbit DRAM line in U.S. (NEC Corp.; dynamic random access memory) Highbeam Business, October 24, 1994
- ↑ NEC, Samsung sampling 64-Mbit DRAMs Highbeam Business, April 17, 1995
- ↑ Alliance unwraps 256-Mbit DRAM. (IBM Corp, Toshiba Corp, Siemens AG) Highbeam Business, June 12, 1995
- ↑ International chip trio delivers memory jump. (Siemens AG, IBM Corp. and Toshiba Corp. plan to develop a 256-Mbit dynamic random access memory chip)(Tech Trends)(Brief Article) Highbeam Business, July 3, 1995
- ↑ Breaking the gigabit barrier, DRAMs at ISSCC portend major system-design impact. (dynamic random access memory; International Solid-State Circuits Conference; Hitachi Ltd. and NEC Corp. research and development) Highbeam Business, January 9, 1995
- ↑ Samsung announces 16GB DDR4 DIMM to be released in 2014 TweakTown, July 5, 2012
- 1 2 3 Smith, Kevin (August 11, 1983). "Image processor handles 256 pixels simultaneously". Electronics.
- ↑ "Cell chip: Hit or hype?" by Michael Kanellos 2005